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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

共 2826 条记录，以下是511-520 订阅

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AutomaticDetection of the bolt looseness based on digital image processing technology 9

AutomaticDetection of the bolt looseness based on digital im...

引用

9th international conference on Structural Health Monitoring of Intelligent Infrastructure: Transferring Research into Practice, SHMII 2019

作者： Huo, L. Liu, Y. Li, H. Dalian University of Technology China

Bolted joints are important forms of connections in bridges, buildings, pipelines, transmission towers and other civil structures. Loose structure may cause damage to the connection structure of the system or even collapse, so surveillance and inspection bolted structure is very important. Usually, the inspector can visually inspect loose bolts to assess health. However, the traditional visual inspection is time consuming, cumbersome and inaccurate. With the development of digital image processing technology, it can be applied fast, safe and accurate way to detect large-scale structure of the loose bolts. this paper proposes an automatic detection method of bolt looseness, in which all testing processes are automatically completed, including image preprocessing, edge recognition, image correction to the parallel plane of the lens and angle calculation. the applicability of this method was experimentally verified by NDI Optotrack three-dimensional measurement system(NDI), and the proposed method error was less than5.5%, which suggested that this method could accurately detect the looseness of bolts. © 2019 9th international conference on Structural Health Monitoring of Intelligent Infrastructure: Transferring Research into Practice, SHMII 2019 - conference Proceedings. All rights reserved.

关键词： Bolts

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Design and Verification of High-Speed Radix-2 Butterfly FFT Module for DSP Applications

Design and Verification of High-Speed Radix-2 Butterfly FFT ...

引用

international conference on Trends in Electronics and Informatics (ICEI)

作者： Utsav Kumar Malviya Government Engineering College Bilaspur India

ISBN: (数字)9781728155180

ISBN: (纸本)9781728155197

Digital signal processing (DSP) processor is a key element of 4th Generation (4G) communication and Fast Fourier Transform (FFT) is an important operation of the modern Digital signal Processor (DSP). this work design an area and speed optimized FFT module for the DSP processor. Real-time computation of signals must meet real-time scenarios and highly requires to make computation faster as possible, hence a fast FFT proposed. Two types of methods can be used for FFT operation: first is Decimation in time (DIT) and second is Decimation in frequency (DIF). the operational speed of these algorithms depends on the multipliers used for computation. Multipliers in the FFT process are the key factor for the speed performance and if multiplier modifies in terms of area and speed overall FFT processor also performance gets an increase. this work design FFT processor with Vedic multiplier and new semi-pipelined Fast Fourier transform (SPFFT) with modified multiplication arrangement gave a provide area optimized hardware architecture. In conventional method, radix-2 2 had been used only for single-path delay feedback architectures. Later with many types of research works radix, 22 was extended to multipath delay commutation (MDC) architectures. this work design is provided for parallel operation of value 16 signal samples, Xilinx Vivado EDA is used for the implementation of this work. for emulation Zynq-7 FPGA board used.

关键词： Adders Random access memory Pipeline processing conferences Market research Informatics Digital signal processing

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A Post-processing Approach in Moving Objects Detection via Feature Pyramid Networks 9

A Post-Processing Approach in Moving Objects Detection via F...

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9th international conference on parallel architectures, algorithms and Programming (PAAP)

作者： Lin, Li Wang, Bin Gu, Yinjuan Shanghai Univ Shanghai Inst Adv Commun & Data Sci Shanghai Peoples R China Shanghai Univ Sch Commun & Informat Engn Shanghai Peoples R China

ISBN: (纸本)9781538694039

Recent work has shown that Convolutional Neural Networks (CNNs) have great ability to deal with classification problems in pattern recognition field. Moving objects detection, regarding as a classification process, labels every pixel as a foreground pixel or a background pixel. In this paper, we proposed an effective post-processing approach, Residual Background Networks (ResBGNets), to improve the accuracy of moving objects detection in video sequences. Instead of learning the ground truth directly, our model learns the residual pictures between the results of existing methods and the ground truth. It benefits to understand the hidden character of each algorithm and correct the misclassification. Inside ResBGNets, we build Feature Pyramid Networks (FPN) to combine spatial information of the low-resolution level with semantical features of high-level of the high-resolution level. Evaluation performed on the 2014 CDnet dataset reveals that through our approach, most of the existing background subtraction methods can get better detection results and a significant higher FM score.

关键词： Moving objects detection convolutional neural networks background subtraction residual pictures feature pyramids

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Multi-agent Supply Planning Methods Allowing the Real-Time Performance of the Supply Network Management Systems 1

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9th international conference on Industrial Applications of Holonic and Multi-Agent Systems (HoloMAS)

作者： Tsarev, Alexander ICCS RAS Samara Russia

ISBN: (数字)9783030278786

ISBN: (纸本)9783030278786;9783030278779

the paper deals with the questions of how to develop the automated planning systems that are fast enough to be used in real-time management of supply networks, considering the manual plan corrections by the users. Several practical situations and planning system use cases are considered. the paper proposes several methods that allow the increase of the data processing speed in practical cases. the methods include parallel data processing, dynamic control of the solutions space depth search, self-regulation of the system behavior based of the specifics of the data processed.

关键词： Distributed planning Self-regulation parallel processing Coordination Performance Real-time scheduling Real-time management Multi-agent planning Supply network Supply chain

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EMBA: Efficient Memory Bandwidth Allocation to Improve Performance on Intel Commodity Processor 19

EMBA: Efficient Memory Bandwidth Allocation to Improve Perfo...

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48th international conference on parallel processing (ICPP)

作者： Xiang, Yaocheng Ye, Chencheng Wang, Xiaolin Luo, Yingwei Wang, Zhenlin Peking Univ Shenzhen Peoples R China Huazhong Univ Sci & Technol Wuhan Hubei Peoples R China Michigan Technol Univ Houghton MI 49931 USA Peking Univ SECE Shenzhen Key Lab Cloud Comp Technol & Applicat Shenzhen Peoples R China Pengcheng Lab Shenzhen Peoples R China Huazhong Univ Sci & Technol Natl Engn Res Ctr Big Data Technol & Syst Serv Comp Technol & Syst Lab Cluster & Grid Comp LabSch Comp Sci & Technol Wuhan Hubei Peoples R China

ISBN: (纸本)9781450362955

On multi-core processors, contention on shared resources such as the last level cache (LLC) and memory bandwidth may cause serious performance degradation, which makes efficient resource allocation a critical issue in data centers. Intel recently introduces Memory Bandwidth Allocation (MBA) technology on its Xeon scalable processors, which makes it possible to allocate memory bandwidth in a real system. However, how to make the most of MBA to improve system performance remains an open question. In this work, (1) we formulate a quantitative relationship between a program's performance and its LLC occupancy and memory request rate on commodity processors. (2) Guided by the performance formula, we propose a heuristic bound-aware throttling algorithm to improve system performance and (3) we further develop a hierarchical clustering method to improve the algorithm's efficiency. (4) We implement these algorithms in EMBA, a low-overhead dynamic memory bandwidth scheduling system to improve performance on Intel commodity processors. the results show that, when multiple programs run simultaneously on a multi-core processor whose memory bandwidth is saturated, the programs with high memory bandwidth demand usually use bandwidth inefficiently compared with programs with medium memory bandwidth demand from the perspective of CPU performance. By slightly throttling the former's bandwidth, we can significantly improve the performance of the latter. On average, we improve system performance by 36.9% at the expense of 8.6% bandwidth utilization rate.

关键词： Memory bandwidth allocation Multi-core architectures

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Modern Code Applied in Stencil in Edge Detection of an Image for Architecture Intel Xeon Phi KNL 5th

Modern Code Applied in Stencil in Edge Detection of an Image...

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5th international conference on Technologies and Innovation (CITI)

作者： Hernandez-Hernandez, Mario Luis Hernandez-Hernandez, Jose Rodriguez Maldonado, Edilia Herrera Miranda, Israel Autonomous Univ Guerrero Engn Fac Chilpancingo Mexico TecNM Technol Inst Chilpancingo Chilpancingo Mexico Autonomous Univ Guerrero Govt & Publ Management Fac Chilpancingo Mexico

ISBN: (纸本)9783030349899;9783030349882

Modern, high-performance computers are built with a combination of heterogeneous resources, including multi-core and many cores processors, large cache, fast memory, mesh communication between large processes bandwidth, as well as high support for Input/Output capabilities. In order to achieve the best hardware results it is necessary to design highly-performance parallel software with faster modern code that could take full advantage of the vast amount of resources of today's modern machines. Code modernization encompasses a wide range of activities that aim to improve the performance of highly parallel software. Code modernization is an issue that is being discussed more and more in the field of parallel software development. In this context, the experimentation with Stencil codes through a series of strategies for reorganizing code and algorithms, has shown to increase thread parallelism, vector/SIMD operations and compute intensity in modern architectures. For example, with the use of Stencil codes we have achieved a better performance in image edge detection by a factor of three faster than we could achieved with a standard processor.

关键词： Modern code Stencil Edge detection KNL Image processing

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parallelization of Variable Rate Decompression through Metadata

Parallelization of Variable Rate Decompression through Metad...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Lennart Noordsij Steven van der Vlugt Mohamed A. Bamakhrama Zaid Al-Ars Peter Lindstrom ASML Netherlands Synopsys Corporation Netherlands TU Delft Netherlands Lawrence Livermore National Laboratory United States of America

Data movement has long been identified as the biggest challenge facing modern computer systems9; designers. To tackle this challenge, many novel data compression algorithms have been developed. Often variable rate ... 详细信息

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165837

Data movement has long been identified as the biggest challenge facing modern computer systems' designers. To tackle this challenge, many novel data compression algorithms have been developed. Often variable rate compression algorithms are favored over fixed rate. However, variable rate decompression is difficult to parallelize. Most existing algorithms adopt a single parallelization strategy suited for a particular HW platform. Such an approach fails to harness the parallelism found in diverse modern HW architectures. We propose a parallelization method for tiled variable rate compression algorithms that consists of multiple strategies that can be applied interchangeably. this allows an algorithm to apply the strategy most suitable for a specific HW platform. Our strategies are based on generating metadata during encoding, which is used to parallelize the decoding process. To demonstrate the effectiveness of our strategies, we implement them in a state-of-the-art compression algorithm called ZFP. We show that the strategies suited for multicore CPUs are different from the ones suited for GPUs. On a CPU, we achieve a near optimal decoding speedup and an overhead size which is consistently less than 0.04% of the compressed data size. On a GPU, we achieve average decoding rates of up to 100 GiB/s. Our strategies allow the user to make a trade-off between decoding throughput and metadata size overhead.

关键词： Decoding Metadata Compression algorithms Encoding Data transfer Acceleration Multicore processing

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Distributing Sparse Matrix/Graph Applications in Heterogeneous Clusters - an Experimental Study

Distributing Sparse Matrix/Graph Applications in Heterogeneo...

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international conference on High Performance Computing

作者： Charilaos Tzovas Maria Predari Henning Meyerhenke Humboldt-Universität zu Berlin Berlin Germany

Many problems in scientific and engineering applications contain sparse matrices or graphs as main input objects, e.g., numerical simulations on meshes. Large inputs are abundant these days and require parallel processing for memory size and speed. To optimize the execution of such simulations on cluster systems, the input problem needs to be distributed suitably onto the processing units (PUs). More and more frequently, such clusters contain different CPUs or a combination of CPUs and GPUs. this heterogeneity makes the load distribution problem quite challenging. Our study is motivated by the observation that established partitioning tools do not handle such heterogeneous distribution problems as well as homogeneous ones. In this paper, we first formulate the problem of balanced load distribution for heterogeneous architectures as a multiobjective, single-constraint optimization problem. We then split the problem into two phases and propose a greedy approach to determine optimal block sizes for each PU. these block sizes are then fed into numerous existing graph partitioners, for us to examine how well they handle the above problem. One of the tools we consider is an extension of our own previous work (von Looz et al., ICPP'18) called Geographer. Our experiments on well-known benchmark meshes indicate that only two tools under consideration are able to yield good quality. these two are ParMetis (both the geometric and the combinatorial variant) and Geographer. While ParMetis is faster, Geographer yields better quality on average.

关键词： Greedy algorithms High performance computing Memory management Tools parallel processing Numerical simulation Numerical models

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9th Annual international conference on Biologically Inspired Cognitive architectures, BICA 2018

9th Annual International Conference on Biologically Inspired...

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9th Annual international conference on Biologically Inspired Cognitive architectures, BICA 2018

ISBN: (纸本)9783319993157

the proceedings contain 47 papers. the special focus in this conference is on . the topics include: Experimental Model of Study of Consciousness at the Awakening: FMRI, EEG and Behavioral Methods;a Temporal-Causal Modeling Approach to the Dynamics of a Burnout and the Role of Physical Exercise;adaptive Neuro-Fuzzy Inference System Used to Classify the Measurements of Chemical Sensors;association Rules Mining for Predictive Analytics in IoT Cloud System;visual Priming in a Biologically Inspired Cognitive Architecture;neural 2D Cart and Pole Control and Forward Model;a Formal Model of the Mechanism of Semantic Analysis in the Brain;group Determination of Parameters and Training with Noise Addition: Joint Application to Improve the Resilience of the Neural Network Solution of a Model Inverse Problem to Noise in Data;a Computational Model for Supporting Access Policies to Semantic Web;narRob: A Humanoid Social Storyteller with Emotional Expression Capabilities;basic Language Learning in Artificial Animals;the Concept of Functional Tractography Method for Cognitive Brain Studies;Feasibility Study and Practical Applications Using Independent Core Observer Model AGI Systems for Behavioral Modification in Recalcitrant Populations;web-Analytics Based on Fuzzy Cognitive Maps;information Approach in the Problems of Data processing and Analysis of Cognitive Experiments;network Modeling Environment for Supporting Families of Displaced Concepts;designing an Emotionally-Intelligent Assistant of a Virtual Dance Creator;the Method of Statistical Estimation of the Minimum Number of Tests for Reliable Evaluation of the Robotic Multi-channel Control Systems Quality;neurotransmitters Level Detection Based on Human Bio-Signals, Measured in Virtual Environments.

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On the Convergence Acceleration and parallel Implementation of Continuation in Disconnected Bifurcation Diagrams for Large-Scale Problems 13th

On the Convergence Acceleration and Parallel Implementation ...

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13th international Scientific conference on parallel Computational Technologies (PCT)

作者： Evstigneev, Nikolay M. Russian Acad Sci Inst Syst Anal Fed Res Ctr Comp Sci & Control Moscow Russia

ISBN: (纸本)9783030281632;9783030281625

the automated construction of disconnected bifurcation diagrams for large-scale steady-state problems is a difficult task. Standard continuation methods are not suited for Krylov-type solvers when dealing with disconnected solutions and, to allow branch switching, they require that the vectors that span the linear operator kernel at bifurcation points be known. An alternative approach to Krylov-type solvers was suggested by Farrell, Beentjes, and Birkisson in 2016, based on the idea of solution deflation. In this paper, we modify the aforementioned method by changing the algorithm to accelerate convergence and rearranging it to be more suited for parallel architectures together with the pseudo-arclength continuation method. We provide a detailed explanation of the corresponding serial and parallel algorithms. Furthermore, we demonstrate the efficiency and correctness of the algorithms by constructing bifurcation diagrams for the 1D Bratu problem and the stationary Kuramoto-Sivashinsky equation considered in 1D and 2D.

关键词： Newton's methods Continuation Solution deflation Automated bifurcation analysis Disconnected bifurcations Branch switching Krylov methods

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