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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

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Profit-driven stochastic scheduling considering discounted cash flows under Industry 4.0 9

Profit-driven stochastic scheduling considering discounted c...

引用

9th IFAC/IFIP/IFORS/IISE/INFORMS conference on Manufacturing Modelling, Management and Control (IFAC MIM)

作者： Liu, Ming Liu, Xin Tongji Univ Sch Econ & Management Shanghai 200092 Peoples R China

Industry 4.0 introduces new paradigm change in manufacturing systems, i.e., a collective term of value chain organization, to cope with unforeseen and negative events more efficiently. Since scheduling is crucial in the manufacturing systems, stochastic scheduling is thus a hot and challenging research topic. Job processing times are usually assumed to be stochastic due to various factors. this work studies a parallel machine scheduling problem with uncertain processing times, in which the penalty cost incurred by job rejection arises at the beginning and the revenue of processing a job is received once the job is completed. Besides, based on the cooperation between production, marketing and finance, the capital time value is considered by discounting the cash flows. the pursued financial objective is to maximize the the net present value (NPV) of the total profit, including the negative penalty cost for rejecting jobs and the expected revenue for processing jobs. For the problem, a two-stage stochastic programming formulation with an exponential objective function is proposed. the second-order Taylor series expansion approximation for the objective function is first applied, and the classic sample average approximation (SAA) method is then developed. A case study is conducted to illustrate the applicability of the proposed method. (C) 2019, IFAC (international Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： parallel machine scheduling Stochastic optimization Uncertain processing times Discounted cash flows

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Performance Improvement of Deep Learning architectures for Phonocardiogram Signal Classification using Fast Fourier Transform

Performance Improvement of Deep Learning Architectures for P...

引用

international conference on Advanced Computer Control, ICACC

作者： P. Gopika V. Sowmya E.A. Gopalakrishnan K.P. Soman Center for Computational Engineering and Networking Amrita Vishwa Vidyapeetham Coimbatore India

Phonocardiogram known as PCG plays a significant role in the early diagnosis of cardiac abnormalities. Phonocardiogram can be used as initial diagnostics tool in remote applications due to its simplicity and cost effectiveness. Instead of disease specific approach, the proposed work aims for the single architecture that could diagnose different cardiac abnormality from the PCG signals collected from various sources. Our study also shows the effectiveness of using Fast Fourier Transform (FFT) in signal processing applications. It avoids the trivial preprocessing and feature extraction mechanisms with the promising results.

关键词： diseases fast Fourier transforms feature extraction learning (artificial intelligence) medical signal processing neural nets phonocardiography signal classification

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Massively parallel Computation of Linear Recurrence Equations with Graphics processing Units 18

Massively Parallel Computation of Linear Recurrence Equation...

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18th international conference on Embedded Computer Systems - architectures, Modeling, and Simulation (SAMOS)

作者： Sung, Wonyong Lee, Dong-hwan Hwang, Kyuyeon Seoul Natl Univ Dept Elect Engn & Comp Sci Seoul South Korea

ISBN: (纸本)9781450364942

Graphics processing units (GPUs) show very high performance when executing many parallel programs;however their use in solving linear recurrence equations is considered difficult because of the sequential nature of the problem. Previously developed parallel algorithms, such as recursive doubling and multi-block processing, do not show high efficiency in GPUs because of poor scalability with the number of threads. In this work, we have developed a highly efficient GPU-based algorithm for recurrences using a thread-level parallel (TLP) approach, instead of conventional thread-block level parallel (TBLP) methods. the proposed TLP method executes all of the threads as independently as possible to improve the computational efficiency and employs a hierarchical structure for inter-thread communication. Not only constant but also time-varying coefficient recurrence equations are implemented on NVIDIA GTX285, GTX580 and GTX TITAN X GPUs, and the performances are compared with the results on single-core and multi-core SIMD CPU-based PCs.

关键词： Graphics processing unit (GPU) massively parallel processing linear recurrence equation prefix-sum scan

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Dependency Parsing of Natural Russian Language with Usage of Semantic Mapping Approach 9

Dependency Parsing of Natural Russian Language with Usage of...

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9th Annual international conference of the Biologically-Inspired-Cognitive-architectures-Society (BICA) held as part of the Joint Multi-conference on Human-Level Artificial Intelligence (HLAI)

作者： Balandinaa, Anita Kostkina, Anastasiya Chernyshov, Artem Klimov, Valentin V. Natl res Nucl Univ MEPhI Moscow Russia

this article discusses the practical implementation of a linguistic processor that solves the task of parsing dependencies. Within this paper, we investigated various modern developments on the ability to adequately parse natural language sentences in Russian. As a result, we suggest the new method of dependency parsing based on BiLSTM neural networks. the comparative analysis showed that suggested method shows the best results than other parsers. We are going to improve our algorithm by appending the semantic analysis with the usage of semantic mapping for better understanding the intentions of sentences. (C) 2018 the Authors. Published by Elsevier B.V. this is an open access article under the CC BY-NC-ND license (https://***/licenses/by-nc-nd/4.0/) Peer-review under responsibility of the scientific committee of the 9th Annual international conference on Biologically Inspired Cognitive architectures.

关键词： dependency parsing natural language processing natural language understanding semantic map

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Architecture of parallel CRC Encoder using State Space Transformations 9

Architecture of Parallel CRC Encoder using State Space Trans...

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9th international conference on Computing, Communication and Networking Technologies (ICCCNT)

作者： Prabha, Lekshmi S. Geethu, R. S. Amrita Vishwa Vidyapeetham Dept Elect & Commun Engn Amritapuri India

ISBN: (纸本)9781538644300

Linear Feedback shift Registers (LFSRs) are widely used in encoders like Cyclic Redundancy Check (CRC) for generating error detecting codes. In order to achieve high speed communication, parallel processing is performed in the serial CRC. Since this method increases the circuit complexity, the speed gets limited. State space transformation is a method that can be used to reduce the circuit complexity. therefore, an efficient transformation matrix is needed in this method. In this paper, a method to construct a transformation matrix and an approximate searching algorithm to generate certain vectors, which are used in transformation matrix are implemented.

关键词： LFSR CRC encoder parallel CRC State Space Transformation Approximate Search Algorithm

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Distributionally robust parallel machine ScheLoc problem under service level constraints 9

Distributionally robust parallel machine ScheLoc problem und...

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9th IFAC/IFIP/IFORS/IISE/INFORMS conference on Manufacturing Modelling, Management and Control (IFAC MIM)

作者： Liu, Ming Liu, Xin Tongji Univ Sch Econ & Management Shanghai 200092 Peoples R China

Scheduling-Location (ScheLoc) problem is relatively new and has received a lot attention. Such a problem focuses on integrating the tactical-level decision (i.e., selecting locations for machines) and the operational-level decision (i.e., schedule of the jobs). Especially, the release time depends on the distance between the job storage location and its processing machine, as each job should be transported to the machine location for processing. the existing researches considering the ScheLoc problem are limited, and most of them focus on the deterministic settings. In practice, job processing times are usually uncertain, and the probability distribution of the uncertain processing times may not be exactly estimated, due to various factors. this work investigates a parallel machine ScheLoc problem under stochastic processing times with only partial distributional information (i.e., the mean and covariance matrix), to minimize the cost for operating machines and control the service level at the same time. the service level in this work is measured by the probability of ensuring no tardy job. For the problem, a distributionally robust formulation is first proposed, in which the service level is restricted with a joint chance constraint. By applying a popular approximation method, an approximated mixed integer second-order cone programming (MI-SOCP) model is then developed. A case study is conducted and reported, to illustrate the applicability of the MI-SOCP model. (C) 2019, IFAC (international Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： ScheLoc problem Uncertain processing times Distributionally robust optimization Service level

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A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable architectures 28

A Configuration Data Multicasting Method for Coarse-Grained ...

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28th international conference on Field Programmable Logic and Applications (FPL)

作者： Kojima, Takuya Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

this paper proposes a novel configuration data compression technique for coarse-grained reconfigurable architectures (CGRAs). the proposed technique is based on a multicast configuration technique called RoMultiC, which reduces the configuration time by multicasting the same data to multiple PEs(processing Elements) with two bit-maps. Scheduling algorithms for an optimizing the order of multicasting have been proposed. In general, configuration data for CGRAs can be divided into some fields like machine code formats. the proposed scheme confines a part of fields for multicasting so that the possibility of multicasting more PEs can be increased. this paper analyzes algorithms to find a configuration pattern which maximizes the number of multicasted PEs. We implemented the proposed scheme to CMA (Cool Mega Array), a straight forward CGRA as a case study. Experimental results show that the proposed method achieves 40.0% smaller configuration for an image processing application at maximum. Furthermore, it achieves 35.6% reduction of the power consumption for the configuration with a negligible area overhead.

关键词： Multicast communication Multicast algorithms Arrays Power demand parallel processing Hardware

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Criticality-aware Design Space Exploration for Mixed-Criticality Embedded Systems 18

Criticality-aware Design Space Exploration for Mixed-Critica...

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9th ACM/SPEC international conference on Performance Engineering (ICPE)

作者： Muttillo, Vittoriano Valente, Giacomo Pomante, Luigi Ctr Excellence DEWS Via Vetoio 1 Laquila Italy

this work(1) focuses on Design Space Exploration for embedded systems based on heterogeneous parallel architectures and subjected to mixed-criticality constraints. In particular, it presents a criticality-aware evolut... 详细信息

ISBN: (纸本)9781450356299

关键词： HW/SW Co-Design Heterogeneous parallel Systems Design Space Exploration Mixed-Criticality Systems

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GPU implementation of ConeTorre algorithm for fluid dynamics simulation 1

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15th international conference on parallel Computing Technologies, PaCT 2019

作者： Levchenko, Vadim Zakirov, Andrey Perepelkina, Anastasia Keldysh Institute of Applied Mathematics 4 Miusskaya Sq. Moscow Russia Kintech Lab Ltd. Moscow Russia

ISBN: (数字)9783030256364

ISBN: (纸本)9783030256357

LRnLA algorithms allow simulation of large problems with performance that exceeds the memory-bound limit of the traditional stepwise algorithms, that is, algorithms without any kind of temporal blocking. We show how the ConeTorre LRnLA algorithm that was successfully implemented for various CPU codes may be ported to work with CUDA framework and implemented the Lattice-Boltzmann Method (LBM) for fluid dynamics. As the standard tools and guidelines do not comply with the LRnLA paradigm, we have performed manual optimization of the communication between main memory levels of GPU and reduce overhead for data access patterns. We have made the performance estimate of the LRnLA implementation with the use of the Roofline model. the computation remains memory-bound, but with the ConeTorre algorithm the operational intensity is increased several times, and the maximum achievable performance for the chosen algorithm parameters is 9 billion cell updates per second on Tesla V100. We have achieved more than 66% of the estimate. As a result, we have developed a fluid simulation code based on the Lattice-Boltzmann method with a performance that surpasses state-of-the-art solutions. © 2019, Springer Nature Switzerland AG.

关键词： Graphics processing unit

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How Much Cache is Enough? A Cache Behavior Analysis for Machine Learning GPU architectures 9

How Much Cache is Enough? A Cache Behavior Analysis for Mach...

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9th international Green and Sustainable Computing conference (IGSC)

作者： Lopez, S. Nimkar, Y. Kotas, G. Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA

ISBN: (纸本)9781538674666

Graphic processing Units (GPUs) are highly parallel, power hungry devices with large numbers of transistors devoted to the cache hierarchy. Machine learning is a target application field of these devices, which take advantage of their high levels of parallelism to hide long latency memory access dependencies. Even though parallelism is the main source of performance in these devices, a large number of transistors is still devoted to the cache memory hierarchy. Upon detailed analysis, we measure the real impact of the cache hierarchy on the overall performance. Targeting Machine Learning applications, we observed that most of the successful cache accesses happen in a very reduced number of blocks. With this in mind, we propose a different cache configuration for the GPU, resulting in 25% of the leakage power consumption and 10% of the dynamic energy per access of the original cache configuration, with minimal impact on the overall performance.

关键词： Graphics processing unit

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