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检索条件"任意字段=9th International Conference on Algorithms and Architectures for Parallel Processing"

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Log(Graph): A Near-Optimal High-Performance Graph Representation 18

Log(Graph): A Near-Optimal High-Performance Graph Representa...

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27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Besta, Maciej Stanojevic, Dimitri Zivic, Tijana Singh, Jagpreet Hoerold, Maurice Hoefler, Torsten Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland

Today9;s graphs used in domains such as machine learning or social network analysis may contain hundreds of billions of edges. Yet, they are not necessarily stored efficiently, and standard graph representations su... 详细信息

ISBN: (纸本)9781450359863

Today's graphs used in domains such as machine learning or social network analysis may contain hundreds of billions of edges. Yet, they are not necessarily stored efficiently, and standard graph representations such as adjacency lists waste a significant number of bits while graph compression schemes such as WebGraph often require time-consuming decompression. To address this, we propose Log(Graph): a graph representation that combines high compression ratios with very low-overhead decompression to enable cheaper and faster graph processing. the key idea is to encode a graph so that the parts of the representation approach or match the respective storage lower bounds. We call our approach "graph logarithmization" because these bounds are usually logarithmic. Our high-performance Log(Graph) implementation based on modern bitwise operations and state-of-the-art succinct data structures achieves high compression ratios as well as performance. For example, compared to the tuned Graph Algorithm processing Benchmark Suite (GAPBS), it reduces graph sizes by 20-35% while matching GAPBS' performance or even delivering speedups due to reducing amounts of transferred data. It approaches the compression ratio of the established WebGraph compression library while enabling speedups of up to more than 2x. Log(Graph) can improve the design of various graph processing engines or libraries on single NUMA nodes as well as distributed-memory systems.

关键词： graph compression graph representation graph layout parallel graph algorithms ILP succinct data structures

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Efficient algorithms of parallel Skyline Join over Data Streams 18th

Efficient Algorithms of Parallel Skyline Join over Data Stre...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zhang, Jinchao Gu, JingZi Cheng, Shuai Li, Bo Wang, Weiping Meng, Dan Chinese Acad Sci Inst Informat Engn Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9783030050511;9783030050504

the issue of finding skyline tuples over multiple relations, more commonly known as the skyline join problem, has been well studied in scenarios in which the data is static. Most recently, it has become a new trend that performing skyline queries on data streams, where tuples arrive or expire in a continuous approach. A few algorithms have been proposed for computing skylines on two data streams. However, those literatures did not consider the inherent parallelism, or employ serial algorithms to solve the skyline query problem, which cannot leverage the multi-core processors. Based on this motivation, in this paper, we address the problem of parallel computing for skyline join over multiple data streams. We developed a Novel Iterative framework based on the existing work and study the inherent parallelism of the Novel Iterative framework. then we propose two parallel skyline join algorithms over sliding windows, NP-SWJ and IP-SWJ. To the best of our knowledge, this is the first paper that addresses parallel computing of skyline join over multiple data streams. Extensive experimental evaluations on real and synthetic data sets show that the algorithms proposed in this paper provide large gains over the state-of-the-art serial algorithm of skyline join over data streams.

关键词： Skyline join Sliding window Data stream parallel computing

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POWER: A parallel-Optimization-Based Framework Towards Edge Intelligent Image Recognition and a Case Study 18th

POWER: A Parallel-Optimization-Based Framework Towards Edge ...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Yang, Yingyi Mai, Xiaoming Wu, Hao Nie, Ming Wu, Hui Guangdong Power Grid Co Ltd Elect Power Res Inst Guangzhou Peoples R China

ISBN: (纸本)9783030050511;9783030050504

To improve the intelligent image recognition abilities of edge devices, a parallel-optimization-based framework called POWER is introduced in this paper. With FPGA (Field-Programmable Gate Array) as its hardware module, POWER provides well extensibility and flexible customization capability for developing intelligent firmware suitable for different types of edge devices in various scenarios. through an actual case study, we design and implement a firmware prototype following the specification of POWER and explore its performance improvement using parallel optimization. Our experimental results show that the firmware prototype we implement exhibits good performance and is applicable to substation inspection robots, which also validate the effectiveness of our POWER framework in designing edge intelligent firmware modules indirectly.

关键词： Edge intelligence Image recognition Framework parallel optimization Substation inspection robot

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GAP-8: A RISC-V SoC for AI at the Edge of the IoT 29

GAP-8: A RISC-V SoC for AI at the Edge of the IoT

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29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Flamand, Eric Rossi, Davide Conti, Francesco Loi, Igor Pullini, Antonio Rotenberg, Florent benini, Luca GreenWaves Technol Villard Bonnot France Univ Bologna DEI Bologna Italy Swiss Fed Inst Technol Integrated Syst Lab Zurich Switzerland

ISBN: (纸本)9781538674796

Current ultra-low power smart sensing edge devices, operating for years on small batteries, are limited to low-bandwidth sensors, such as temperature or pressure. Enabling the next generation of edge devices to process data from richer sensors such as image, video, audio, or multi-axial motion/vibration has huge application potential. However, edge processing of data-rich sensors poses the extreme challenge of squeezing the computational requirements of advanced, machine-learning-based near-sensor data analysis algorithms (such as Convolutional Neural Networks) within the mW-range power envelope of always-ON battery-powered IoT end-nodes. To address this challenge, we propose GAP-8: a multi-GOPS fully programmable RISC-V IoT-edge computing engine, featuring a 8-core cluster with CNN accelerator, coupled with an ultra-low power MCU with 30 mu W state-retentive sleep power. GAP-8 delivers up to 10 GMAC/s for CNN inference (90 MHz, 1.0V) at the energy efficiency of 600 GMAC/s/W within a worst-case power envelope of 75 mW.

关键词： Edge processing Internet of things Convolutional Neural Networks Near Sensor processing parallel architectures

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Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study 29

Invasive Computing for Predictability of Multiple Non-functi...

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29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Sousa, Ericles Witterauf, Michael Brand, Marcel Tanase, Alexandru Hannig, Frank Teich, Juergen Friedrich Alexander Univ Erlangen Numberg FAU Erlangen Germany

ISBN: (纸本)9781538674796

the predictability of non-functional execution qualities is of utmost importance for the successful introduction of multi-core architectures in embedded systems requiring guarantees rather than best effort behavior. Due to the exclusive utilization of claimed resources, invasive computing provides isolation of applications on multi-core systems. this provides composability that allows to characterize and analyze individual applications statically and independent from others. In this paper, we demonstrate the principles of this resource-aware computing paradigm as an enabler for predictability of multiple non-functional properties, i.e., timing and reliability, applied to a cyber-physical system. In particular, we present the application and multi-processor implementation of a reliable and time-predictable acceleration of object detection algorithms for hard real-time control of an inverted pendulum.

关键词： Reliability Runtime Program processors Timing Uncertainty Computer architecture parallel processing"

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Asynchronous parallel Dijkstra's Algorithm on Intel Xeon Phi Processor How to Accelerate Irregular Memory Access Algorithm 18th

Asynchronous Parallel Dijkstra's Algorithm on Intel Xeon Phi...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zhang, Weidong Zhang, Lei Chen, Yifeng Peking Univ EECS Beijing 100871 Peoples R China HuaWei Inc Shenzhen Peoples R China

ISBN: (纸本)9783030050511;9783030050504

As the instruction-level parallelism (ILP) on CPU develops to a rather advanced level, the exploration that whether many-core architecture is applicable for graph algorithms is generating more interests in researchers. However, due to the irregular memory access and the low ratio of computation to memory access, the performance of graph algorithms on many-core architectures has never worked good enough. To obtain outstanding speedup on many-core architecture, first of all, we need to figure out three questions: (i) how to optimize the memory access, (ii) how to minimize the overhead of synchronization, (iii) how to exploit the parallelism in algorithm. Prior works hardly reach the goal if such questions are treated in separated way. throughout this paper, we aim to settle these questions systematically, and try to provide a set of methods of optimizing graph algorithms on many-core architecture. this paper mainly discusses how to accelerate the Single Source Shortest Path (SSSP) problem on Intel Many Integrated Core (MIC) architecture, on which we propose an asynchronous parallel Dijkstra's algorithm. It aims at maximizing parallelism and minimizing overhead of synchronization. Experimental result shows that the MIC architecture could efficiently solve the SSSP problem, and its performance could be sped up by 9.2x compared to the benchmark of DIMACS.

关键词： Single source shortest path parallel algorithm Intel MIC Road network

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A Caching-Based parallel FP-Growth in Apache Spark 1

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Cai, Zhicheng Zhu, Xingyu Zheng, Yuehui Liu, Duan Xu, Lei Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing Peoples R China

ISBN: (数字)9783030050573

ISBN: (纸本)9783030050573;9783030050566

the association-rule-based recommendation is widespread in many big data applications which need quick response to improve user experience. Spark is a widely used distributed computing platform, which accelerates the processing of large-scale distributed data. Developing appropriate distributed algorithm for Spark is essential to decrease the processing time of distributed recommendation. the existing FP-Growth in Spark is a popular parallel recommendation method but getting the best performance only when the memory of machines can accommodate all immediate Resilient Distributed DataSets (RDDs). However, memory of many practice data centers is still not large enough for large data sets. therefore, in this paper, a caching-based parallel FP-Growth is proposed which consists of an integer-based sorting and an RDD-caching strategy to improve the efficiency. Experimental results show that the proposal decreases the execution time by 32.37% on average compared with the existing parallel FP-Growth in Spark. Furthermore, impacts of some important parameters upon the performance of the proposal are analyzed by numerous realistic experiments in Spark.

关键词： Spark parallel FP-Growth Caching strategy

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A parallel Method for All-Pair SimRank Similarity Computation 18th

A Parallel Method for All-Pair SimRank Similarity Computatio...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Huang, Xuan Gao, Xingkun Tang, Jie Wu, Gangshan Nanjing Univ Dept Comp Sci & Technol Nanjing 210023 Peoples R China Nanjing Univ State Key Lab Novel Software Technol Nanjing 210023 Peoples R China

ISBN: (纸本)9783030050511;9783030050504

How to measure SimRank similarity of all-pair vertices in a graph is a very important research topic which has a wide range of applications in many fields. However, computation of SimRank is costly in both time and space, making traditional computing methods failing to handle graph data of ever-growing size. this paper proposes a parallel multi-level solution for all-pair SimRank similarity computing on large graphs. We partition the objective graph first with the idea of modularity maximization and get a collapsed graph based on the blocks. then we compute the similarities between verteices inside a block as well as the similarities between the blocks. In the end, we integrate these two types of similarities and calculate the approximate SimRank simlarities between all vertex pairs. the method is implemented on Spark platform and it makes an improvement on time efficiency while maintaining the effectiveness compared to SimRank.

关键词： SimRank similarity Spark parallel computing

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A new execution model for improving performance and flexibility of CAPE 26

A new execution model for improving performance and flexibil...

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26th Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Van Long Tran Renault, Eric Xuan Huyen Do Viet Hai Ha Univ Paris Saclay CNRS SAMOVAR Telecom SudParis 9 Rue Charles Fourier F-91011 Evry France Hue Ind Coll Hue Vietnam Hue Univ Coll Sci Hue Vietnam Hue Univ Coll Educ Hue Vietnam

ISBN: (纸本)9781538649756

Checkpointing-Aided parallel Execution (CAPE) is a framework that is based on checkpointing technique and serves to automatically translates and execute OpenMP programs on distributed-memory architectures. through some comparisons with MPI, CAPE has demonstrated high-performance and the potential for fully compatibility with OpenMP on distributed-memory systems. However, there is still a long way to improve the performance, flexibility, portability and capability. this paper presents the new execution model for CAPE that improves its performance and makes CAPE even more flexible.

关键词： CAPE Checkpointing OpenMP HPC Distributed Computing parallel computing

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Performance Study of Distributed Big Data Analysis in YARN Cluster 9

Performance Study of Distributed Big Data Analysis in YARN C...

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9th international conference on Information and Communication Technology Convergence (ICTC)

作者： Ahn, HooYoung Kim, Hyunjae You, WoongShik ETRI KSB Convergence Res Dept 218 Gajeong Ro Daejeon 34129 South Korea

ISBN: (纸本)9781538650417

In the 4-th Industrial Revolution era, various intelligent solutions and services have been emerging recently. To provide high quality service in those intelligent applications, the big data should be collected without any loss and comprehensively analyzed. Especially, when using machine and deep learning techniques, the big data processing delays should be minimized in order to guarantee the freshness of models. In this paper, we evaluate the performance of Apache Spark which is one of the most popular big data processing and analysis frameworks. Beyond the performance analysis of Spark in distributed cluster environment, we evaluate the performance of TensorFlowOnSpark which is the promising distributed deep learning framework designed to handle big data efficiently. From the experimental results, we can conclude that Spark on YARN is a solid underlying framework that guarantees the performance and scalability of distributed machine and deep learning by efficiently processing its data and algorithms in a parallel and distributed manner.

关键词： Distributed Machine Learning Distributed Deep Learning Big Data parallel Computing Spark YARN TensorFlow Benchmark

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