In this paper we present an efficient method for 3-D parallel digital filtering using a new parallel filtering algorithm based on the 3-D vector radix fast Hartley transform (3-D VR FH). this method is suitable for hi...
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In this paper we present an efficient method for 3-D parallel digital filtering using a new parallel filtering algorithm based on the 3-D vector radix fast Hartley transform (3-D VR FH). this method is suitable for high resolution/high speed image/video processing. the 3-D parallel algorithm is highly parallel and efficient as it overcomes the overhead and performance limitations of the block filtering method by eliminating the overlapping segments and boundary conditions in parallel filtering applications. It also lifts the restrictions on the input size for high performance in the block-filtering algorithm, as boththe 3-D input data and impulse response of the system are segmented into smaller subsections. these subsections are independent and can be simultaneously processed. the algorithm's structure and mathematical derivation are given and the performance of the algorithm is tested and presented using a parallel processing system with 4-DSP processors.
Given n malleable and non-preemptable parallel jobs that arrive for execution at time 0, we examine and compare two job scheduling strategies that allocate m identical processors among the n competing jobs. In all cas...
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Given n malleable and non-preemptable parallel jobs that arrive for execution at time 0, we examine and compare two job scheduling strategies that allocate m identical processors among the n competing jobs. In all cases, n<m. the first strategy is based on the heuristic paradigm of equipartitioning, and the second is based on the notion of marginal analysis. Equipartitioning uses no a priori information when processor allocations are made to parallel jobs. Marginal analysis, on the other hand, assumes full a priori information in order to maximize processor utility. In this paper, we compare both strategies with respect to average time-to-completion (system performance) and overall time-to-completion (system efficiency). Using a simple job model characterized by sequential time-tocompletion and degree of parallelism, it is demonstrated via simulation that in most cases, the uninformed strategy of equipartitioning outperforms marginal analysis with respect to system performance and without a commensurate degradation in system efficiency.
A modular strategy for scheduling iterative computations is proposed. An iterative computation is represented using a cyclic task-graph. the cyclic task-graph is transformed into an acyclic task-graph. this acyclic ta...
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A modular strategy for scheduling iterative computations is proposed. An iterative computation is represented using a cyclic task-graph. the cyclic task-graph is transformed into an acyclic task-graph. this acyclic task-graph is subsequently scheduled using one of the many well-known and high-quality static scheduling strategies from the literature. Graph unfolding is not employed and the generated schedules therefore require less memory than schedules generated through graph unfolding. Further, the number of iterations does not need to be known at compile-time. the effectiveness of the approach is compared to other methods including a graph unfolding strategy. In addition, the paper experimentally quantifies how the task transformation affects the make-span of the schedules.
the event based architectural style has been recognized as fostering the development of large-scale and complex systems by loosely coupling their components. It is therefore increasingly deployed in various environmen...
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New characteristics for e-commerce applications, such as highly distributed data and unpredictable system nature, require us to revisit query processing for distributed database systems. As join operations involve rel...
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this paper provides a high performance interconnection network that can provide high bandwidth and low latency communication on a custom gigabit crossbar *** implementation consists of the high-speed switch th-Switch,...
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this paper provides a high performance interconnection network that can provide high bandwidth and low latency communication on a custom gigabit crossbar *** implementation consists of the high-speed switch th-Switch,the VIA-supported NIC th-NIC and protocol software th-VIA complied with VIA. th-Switch uses circuit-switching technique instead of packet-switching to reduce the communication *** design and implementation of th-Net's communication mechanism is based on the VIA specification that the data transferring can be performed directly at the user application level,bypassing the operating system kernel,to reduce the communication *** design and implementation details are discussed in this paper.
Given n malleable and non-preemptable parallel jobs that arrive for execution at time 0,we examine and compare two job scheduling strategies that allocate m identical processors among the n competing *** all cases,n≤...
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Given n malleable and non-preemptable parallel jobs that arrive for execution at time 0,we examine and compare two job scheduling strategies that allocate m identical processors among the n competing *** all cases,n≤*** first strategy is based on the heuristic paradigm of equipartitioning,and the second is based on the notion of marginal *** uses no a priori information when processor allocations are made to parallel *** analysis,on the other hand,assumes full a priori information in order to maximize processor *** this paper,we compare both strategies with respect to average time-to-completion(system performance) and overall time-to-completion(system efficiency).Using a simple job model characterized by sequential time-to-completion and degree of parallelism,it is demonstrated via simulation that in most cases,the uninformed strategy of equipartitioning outperforms marginal analysis with respect to system performance and without a commensurate degradation in system efficiency.
In this paper we present an efficient method for 3-D parallel digital filtering using a new parallel filtering algorithm based on the 3-D vector radix fast Hartley transform(3-D VR FHT).this method is suitable for hig...
详细信息
In this paper we present an efficient method for 3-D parallel digital filtering using a new parallel filtering algorithm based on the 3-D vector radix fast Hartley transform(3-D VR FHT).this method is suitable for high resolution/high speed image/video *** 3-D parallel algorithm is highly parallel and efficient as it overcomes the overhead and performance limitations of the block filtering method by eliminating the overlapping segments and boundary conditions in parallel filtering *** also lifts the restrictions on the input size for high performance in the block-filtering algorithm,as boththe 3-D input data and impulse response of the system are segmented into smaller *** subsections are independent and can be simultaneously *** algorithm's structure and mathematical derivation are given and the performance of the algorithm is tested and presented using a parallel processing system with 4-DSP processors.
A modular strategy for scheduling iterative computations is *** iterative computation is represented using a cyclic *** cyclic task-graph is transformed into an acyclic *** acyclic task-graph is subsequently scheduled...
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A modular strategy for scheduling iterative computations is *** iterative computation is represented using a cyclic *** cyclic task-graph is transformed into an acyclic *** acyclic task-graph is subsequently scheduled using one of the many well-known and high-quality static scheduling strategies from the *** unfolding is not employed and the generated schedules therefore require less memory than schedules generated through graph ***,the number of iterations does not need to be known at *** effectiveness of the approach is compared to other methods including a graph unfolding *** addition,the paper experimentally quantifies how the task transformation affects the make-span of the schedules.
In third-generation (3G) wireless data networks, mobile users experiencing poor channel quality usually have low data-rate connections withthe base-station. Providing service to low data-rate users is required for ma...
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ISBN:
(纸本)9781581137538
In third-generation (3G) wireless data networks, mobile users experiencing poor channel quality usually have low data-rate connections withthe base-station. Providing service to low data-rate users is required for maintaining fairness, but at the cost of reducing the cell's aggregate throughput. In this paper, we propose the Unified Cellular and Ad-Hoc Network (UCAN) architecture for enhancing cell throughput, while maintaining fairness. In UCAN, a mobile client has both 3G cellular link and IEEE 802.11-based peer-to-peer links. the 3G base station forwards packets for destination clients with poor channel quality to proxy clients with better channel quality. the proxy clients then use an ad-hoc network composed of other mobile clients and IEEE 802.11 wireless links to forward the packets to the appropriate destinations, thereby improving cell throughput. We refine the 3G base station scheduling algorithm so that the throughput gains of active clients are distributed proportional to their average channel rate, thereby maintaining fairness. Withthe UCAN architecture in place, we propose novel greedy and on-demand protocols for proxy discovery and ad-hoc routing that explicitly leverage the existence of the 3G infrastructure to reduce complexity and improve reliability. We further propose a secure crediting mechanism to motivate users to participate in relaying packets for others. through extensive simulations with HDR and IEEE 802.11b, we show that the UCAN architecture can improve individual user's throughput by up to 310% and the aggregate throughput of the HDR downlink by up to 60%.
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