作者:
Torsten SchaubSchool of Computing Science
Simon Fraser University Burnaby Canada and The Institute for Integrated and Intelligent Systems Griffith University Brisbane Australia and Universität Potsdam Institut für Informatik Potsdam Germany
the field of knowledge representation and reasoning has been going through a methodological shift during recent years. While the past was dominated by query-oriented reasoning, model-based techniques become more and m...
ISBN:
(纸本)9783540789680
the field of knowledge representation and reasoning has been going through a methodological shift during recent years. While the past was dominated by query-oriented reasoning, model-based techniques become more and more popular nowadays. this development was primarily driven by the availability of highly efficient Boolean constraint solvers, like satisfiability and answer set solvers. the general idea is to translate an application problem into a logical specification. this specification is in turn passed to a solver, which outputs models representing solutions to the initial application *** talk will provide an introduction to answer set programming (ASP), its proof-theoretic foundations, methodology, implementation techniques along with a glimpse of an exemplary application. Besides knowledge representation and reasoning, ASP has its roots in deductive databases, nonmonotonic reasoning, and logicprogramming. Applications are specified in ASP in terms of sets of logical rules. Modern ASP solvers rely on high-performance Boolean constraint solving techniques, which allow them to tackle application domains consisting of millions of variables. Meanwhile, this approach proved to be an effective tool in a range of applications, like planning, model checking, and bio-informatics.
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. T...
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In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. the algorithm uses device-level gate leakage models for prechar-acterizing register-transfer level (RTL) datapath component library and minimizes the leakage delay product (LDP). the proposed algorithm is tested for several circuits for 45nm CMOS technology node. the experiments show that average gate leakage reduction are 67.7% and 80.8% for SiO{sub}2-SiON and SiO{sub}2-Si{sub}3N{sub}4, respectively.
Transactional Memory (TM) has been proposed as a promising solution to effectively harness the increasing processing power of emerging multi/manycore systems. While there has been considerable research on the design a...
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Transactional Memory (TM) has been proposed as a promising solution to effectively harness the increasing processing power of emerging multi/manycore systems. While there has been considerable research on the design and implementation of TM systems, it remains to be shown how to address the validation challenge of such systems in face of increasing design bugs and dynamic errors. this paper proposes a runtime validation methodology for ensuring the end-to-end correctness of a TM system. We use an extended constraint graph model to capture the correctness of a transactional execution, and provide efficient hardware support to perform online checking of this constraint graph. We describe the design ideas as well as the key optimization techniques to make this approach practical. Experiments based on a state-of-the-art TM system framework show that our design effectively performs system-level runtime validation with relatively small overhead.
Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of the most effective techniques used to ach...
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Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of the most effective techniques used to achieve low power specification. On the other hand, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by single event upsets (SEUs) becomes exponentially greater. Lowering supply voltage to save energy increases soft error rates caused by SEU for two reasons: I) lower voltage makes digital circuits more prone to soft errors and II) reduction in supply voltage, increases the duration of process which increases the chances of being hit by SEU. In this paper, we propose an optimal methodology for DVS on a task graph with consideration of soft error rate. We consider the effects of voltage on SEU and incorporate this dependency in our formulation to develop a new method for energy optimization under SEU constraints. We also propose a convex programming formulation that can be solved efficiently and optimally. We show the effectiveness of our optimal results by simulation on TGFF benchmarks.
We employ the narrowing-based execution mechanism of the functionallogicprogramming language Curry in order to automatically generate a system of test cases for glass-box testing of Curry programs. the test cases fo...
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We propose a new definition and use of a primitive getAllValues, for computing all the values of a non-deterministic expression in a functionallogic program. Our proposal restricts the validity of the argument of get...
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Essential elements of aspect-oriented programming can be formulated as forms of logicprogramming. Extensions of Horn Clause Prolog provide richer abstraction and control mechanisms. Definite clauses that pertain to a...
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ISBN:
(纸本)9783540696087
Essential elements of aspect-oriented programming can be formulated as forms of logicprogramming. Extensions of Horn Clause Prolog provide richer abstraction and control mechanisms. Definite clauses that pertain to a common aspect, and which crosscut other program components, can be encapsulated using the connectives of higher-order intuitionistic logic. the integration or weaving of program fragments can be formulated using normalized forms of proof search in linear logic.
the proceedings contain 23 papers. the topics discussed include: user-definable rule priorities for CHR;detecting defects in Erlang programs using static analysis;practical use of polynomials over the reals in proofs ...
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ISBN:
(纸本)1595937692
the proceedings contain 23 papers. the topics discussed include: user-definable rule priorities for CHR;detecting defects in Erlang programs using static analysis;practical use of polynomials over the reals in proofs of termination;type safe dynamic linking for JVM access control;systematic generation of glass-box test cases for functionallogic programs;mechanized metatheory model-checking;relational semantics for effect-based program transformations with dynamic allocation;higher-order semantic labelling for inductive datatype systems;observing intermediate structures in a parallel lazy functional language;computing with subspaces;real-time rewriting semantics of orc;a larger decidable semiunification problem;local reasoning about storable locks;induction for positive almost sure termination;unfolding in CHR;and nonmonotonic inductive logicprogramming by instance patterns.
Declarative systems, such as logicprogramming, should be ideal to process large data sets efficiently. Unfortunately, the high-level nature of logic-based representations can cause inefficiencies, and may lead in som...
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ISBN:
(纸本)9783540696087
Declarative systems, such as logicprogramming, should be ideal to process large data sets efficiently. Unfortunately, the high-level nature of logic-based representations can cause inefficiencies, and may lead in some cases to unacceptable performance. We discuss how logicprogramming systems can accommodate large amounts of data in main memory. We use a number of real datasets to evaluate performance and discuss how a number of techniques can be used to improve memory scalabality for such datasets.
the proceedings contain 21 papers. the topics discussed include: BAD, a declarative logic-based language for brain modeling;from zinc to design model;inductive logicprogramming by instance patterns;ARMC: the logical ...
ISBN:
(纸本)3540696083
the proceedings contain 21 papers. the topics discussed include: BAD, a declarative logic-based language for brain modeling;from zinc to design model;inductive logicprogramming by instance patterns;ARMC: the logical choice for software model checking with abstraction refinement;the joins concurrency library;HPorter: using arrows to compose parallel processes;coupled schema transformation and data conversion for XML and SQL;aspect-oriented programming in higher-order and linear logic;partial evaluation of pointcuts;quickcheck testing for fun and profit;a constraint programming approach to bioinformatics structural problems;rewriting haskell strings;instantly turning a naive exhaustive search into three efficient searches with pruning;algebraic knowledge discovery using haskell;and applications, implementation and performance evaluation of bit stream programming in Erlang.
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