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检索条件"任意字段=ACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays"

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Memory-to-memory connection structures in FPGAs with embedded memory arrays 97

Memory-to-memory connection structures in FPGAs with embedde...

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Proceedings of the 1997 acm 5th international symposium on field-programmable gate arrays, FPGA

作者： Wilton, Steven J.E. Rose, Jonathan Vranesic, Zvonko G. Univ of British Columbia Vancouver BC Canada

ISBN: (纸本)9780897918015

this paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to multiple memory arrays are often difficult to route, and are often part of the critical path of circuit implementations. the memory-to-memory connection structure proposed in this paper allows for the efficient implementation of these nets, resulting in a reduction in memory access time of up to 25% and a slight improvement in routability.

关键词： Parallel processing systems

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Efficiently supporting fault-tolerance in FPGAs 98

Efficiently supporting fault-tolerance in FPGAs

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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Lach, John Mangione-Smith, William H. Potkonjak, Miodrag UCLA EE Dep Los Angeles CA United States

ISBN: (纸本)9780897919784

While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical design into a set of tiles. In response to a component failure, we capitalize on the unique reconfiguration capabilities of FPGAs and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead.

关键词： field programmable gate arrays

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Folded integer multiplication for fpgas 21

Folded integer multiplication for fpgas

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2021 acm/sigda international symposium on field-programmable gate arrays, FPGA 2021

作者： Langhammer, Martin Pasca, Bogdan Intel Corporation Salisbury United Kingdom Intel Corporation France

ISBN: (纸本)9781450382182

Encryption-especially the key exchange algorithms such as RSA-is an increasing use-model for FPGAs, driven by the adoption of the FPGA as a SmartNIC in the datacenter. While bulk encryption such as AES maps well to generic FPGA features, the very large multipliers required for RSA are a much more difficult problem. Although FPGAs contain thousands of small integer multipliers in DSP Blocks, aggregating them into very large multipliers is very challenging because of the large amount of soft logic required-especially in the form of long adders, and the high embedded multiplier count. In this paper, we describe a large multiplier architecture that operates in a multi-cycle format and which has a linear area/throughput ratio. We show results for a 2048-bit multiplier that has a latency of 118 cycles, inputs data every 9th cycle and closes timing at 377MHz in an Intel Arria 10 FPGA, and over 400MHz in a Stratix 10. the proposed multiplier uses 1/9 of the DSP resources typically used in a 2048-bit Karatsuba implementation, showing a perfectly linear throughput to DSP-count ratio. Our proposed solution outperforms recently reported results, in either arithmetic complexity-by making use of the Karatsuba techniques, or in scheduling efficiency-embedded DSP resources are fully utilized. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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SmartOpt: An industrial strength framework logic synthesis

SmartOpt: An industrial strength framework logic synthesis

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Jang, Stephen Wu, Dennis Jarvin, Mark Chan, Billy Chung, Kevin Mishchenko, Alan Brayton, Robert Xilinx Inc United States University of California Berkeley United States

ISBN: (纸本)9781605584102

In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research in logic synthesis has been fruitful, but these advances have been demonstrated on academic architectures and benchmark designs which are not representative of modern industrial FPGAs. this paper presents a framework (SmartOpt) for mapping complex FPGA architectures to a simple netlist model, which can be supported by academic tools. SmartOpt was applied to leverage the algorithms implemented in the ABC package and to study their relative contributions. this work is integrated into the Xilinx ISE 11.1 software flow for FPGAs and shows significant improvements in both the LUT count and performance of large industrial circuits described in HDL. Xilinx Synthesis Technology (XST) reference flow was compared experimentally against the same flow augmented by SmartOpt. When applied to a set of 20 large industrial Virtex-5 benchmarks ranging from 17K to 69K 6- LUTs, the augmented flow produced 8.3% fewer LUTs and led to 2.1% higher operating frequency while keeping runtimes reasonable. With dual-LUT-merging, the LUT count is reduced by 22.7%, while increasing the operating frequency only by 0.7%. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Towards automated ECOs in FPGAs

Towards automated ECOs in FPGAs

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Andrew Brown, Stephen Zhu, Jianwen Safarpour, Sean Electrical and ComputerEngineering University of Toronto Canada Toronto Technology Center Altera Corporation Canada

ISBN: (纸本)9781605584102

During the FPGA design flow, engineering change orders (ECOs) have become an essential methodology to apply late-stage specification changes and bug fixes. ECOs are beneficial since they are applied directly to a place-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which has an unpredictable impact on the design's final correctness and end costs. As a solution, we introduce an automated method to tackle the ECO problem. Specifically, we introduce a resynthesis technique which can automatically update the functionality of a circuit by leveraging the existing logic within the design;thereby removing the inefficient manual effort required by a designer. Our technique is robust enough to handle a wide range of changes. Furthermore, our technique can successfully make late-stage functional changes while minimally perturbing the place-and-routed netlist: something that is necessary for ECOs. When applied to several benchmarks on Altera's Stratix architecture, we show that our approach can automatically apply ECOs in over 80% of the cases presented. Furthermore, our technique does this with a minimal impact to the circuit performance where on average over 90% of the placement and routing wires remain unchanged. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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An FPGA-based video compressor for H.263 compatible bit streams 01

An FPGA-based video compressor for H.263 compatible bit stre...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Lienhart, G. Männer, R. Lay, R. Noffz, K.H. Dept. for Computer Science V University of Mannheim D-68131 Mannheim Germany

ISBN: (纸本)9781581133417

this paper presents an FPGA architecture for video encoding according to the H.263 standard for video teleconferencing systems. the implementation is based on an off-the-shelf FPGA and is embedded in a PCI plug-in card with on-board SRAM plus external SRAM. the most complex part of the H.263 protocol, a base-line encoder, was implemented. the strategies, which have been applied to build the complex encoding operations, are treated in this paper. the complete application is able to operate at 30 MHz. this leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time operation of several video streams in a single reconfigurable chip. Enhanced coding options can also become implemented with present-day FPGAs. the use of FPGA technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs.

关键词： field programmable gate arrays

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Evolving computer programs using rapidly reconfigurable field-programmable gate arrays and genetic programming 98

Evolving computer programs using rapidly reconfigurable fiel...

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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Koza, John R. Bennett III, Forrest H. Hutchings, Jeffrey L. Bade, Stephen L. Keane, Martin A. Andre, David Stanford Univ Stanford CA United States

ISBN: (纸本)9780897919784

this paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing's H.O.T. Works board) can be exploited to accelerate the time-consuming fitness measurement task of genetic algorithms and genetic programming. this acceleration is accomplished by embodying each individual of the evolving population into hardware in order to perform the fitness measurement task. A 16-step sorting network for seven items was evolved that has two fewer steps than the sorting network described in the 1962 O'Connor and Nelson patent on sorting networks (and the same number of steps as a 7-sorter that was devised by Floyd and Knuth subsequent to the patent and that is now known to be minimal). Other minimal sorters have been evolved.

关键词： field programmable gate arrays

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SMAP: Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

SMAP: Heterogeneous technology mapping for area reduction in...

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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Wilton, Steven J.E. Univ of British Columbia Vancouver Canada

It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. this leads to a waste of chip area for customers that do not use all of the storage provided. this chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement logic. In order to efficiently use the embedded arrays in this way, a technology mapping algorithm that identifies parts of circuits that can be efficiently mapped to an embedded array is required. In this paper, we describe such an algorithm. the new tool, called SMAP, packs as much circuit information as possible into the available memory arrays, and maps the rest of the circuit into four-input lookup-tables. On a set of 29 sequential and combinational benchmarks, the tool is able to map, on average, 60 4-LUTs into a single 2-Kbit memory array. If there are 16 arrays available, it can map, on average, 358 4-LUTs to the 16 arrays.

关键词： field programmable gate arrays

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Timing driven floorplanning on programmable hierarchical targets 98

Timing driven floorplanning on programmable hierarchical tar...

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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Senouci, S.A. Amoura, A. Krupnova, H. Saucier, G. Inst Natl Polytechnique de Grenoble/CSI Grenoble France

ISBN: (纸本)9780897919784

the goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following its hierarchy. the circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. the floorplanning is then guided by this cone structuring and has two innovative features: first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, thus a significant reduction is obtained;second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.

关键词： Timing circuits

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A high-performance FPGA architecture for restricted machines

A high-performance FPGA architecture for restricted machines

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ly, Daniel L. Chow, Paul Department of Electrical and Computer Engineering University of Toronto Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781605584102

ef>Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of is due to the fact that neural networks are usually as software running on general-purpose processors. to implement a neural network in software typically O(n2) problems - as a result, neural networks unable to provide the performance and scalability required non-academic settings. this paper, we investigate how FPGAs can be used take advantage of the inherent parallelism in neural networks provide a better implementation in terms of scalability performance. We will focus on the Restricted machine, a popular type of neural network, because architecture is particularly well-suited to hardware . the proposed, multi-purpose hardware framework designed to reduce the O(n2) problem into an O(n) implementation only requiring O(n) resources. the framework tested on a Xilinx Virtex II-Pro XC2VP70 FPGA at 100MHz. the resources support a Restricted machine of 128 x 128 nodes, which results in computational speed of 1.02 billion connection-updatesper- and a speed-up of 35 fold over an optimized C program running on a 2.8GHz Intel processor. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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