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Square-rich fixed point polynomial evaluation on FPGAs 14

Square-rich fixed point polynomial evaluation on FPGAs

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2014 acm/sigda international symposium on field programmable gate arrays, FPGA 2014

作者： Xu, Simin Fahmy, Suhaib A. McLoughlin, Ian V. Xilinx Asia Pacific Singapore School of Computer Engineering Nanyang Technological University Singapore School of Information Science and Technology University of Science and Technology of China China

ISBN: (纸本)9781450326711

Polynomial evaluation is important across a wide range of application domains, so signicant work has been done on accelerating its computation. the conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial com-putation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. this paper presents an effcient polynomial evaluation algorithm, which reforms the evaluation process to include an increased num-ber of squaring steps. By using a squarer design that is more effcient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 FPGA. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5th degree polynomials.

关键词： field programmable gate arrays (FPGA)

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CMOS continuous-time field programmable analog array

CMOS continuous-time field programmable analog array

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Proceedings of the 1997 acm 5th international symposium on field-programmable gate arrays, FPGA

作者： Looby, C.A. Lyden, C. Univ Coll Cork Ireland

A circuit design for a field programmable Analog Array is presented which improves accuracy and repeatability compared to previous designs. Controlled by a configuration register, continuous-time signals are routed among programmable analog blocks to implement the user's chosen circuit. the configurable connections are realized by CMOS switches and a new innovation is that these are either buffered or nulled to cancel parasitic error. the function blocks are Op-Amps combined with passive networks which allow programmable transfer functions with accuracy insensitive to variations in process parameters and environment. the intended application area is the rapid development of analog circuits which are presently prototyped by PCBs stuffed with Op-Amp and passive components. the concept has been demonstrated on a CMOS IC and the resulting performance shows the feasibility of this approach to general purpose FPAA technology.

关键词： CMOS integrated circuits

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Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation 98

Boolean matching for complex PLBs in LUT-based FPGAs with ap...

引用

Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Cong, Jason Hwang, Yean-Yow Univ of California Los Angeles CA United States

ISBN: (纸本)9780897919784

In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but also can implement some wide functions of more than K variables. We apply previous and develop new functional decomposition methods to match wide functions to PLBs. We can determine exactly whether a given wide function can be implemented with a XC4000 CLB or other three PLB architectures (including the XC5200 CLB). We evaluate functional capabilities of the four PLB architectures on implementing wide functions in MCNC benchmarks. Experiments show that the XC4000 CLB can be used to implement up to 98% of 6-cuts and 88% of 7-cuts in MCNC benchmarks, while two of the other three PLB architectures have a smaller cost in terms of logic capability per silicon area. Our results are useful for designing future logic unit architectures in LUT based FPGAs.

关键词： field programmable gate arrays

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Bit-level optimization for high-level synthesis and FPGA-based acceleration 10

Bit-level optimization for high-level synthesis and FPGA-bas...

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18th acm sigda international symposium on field-programmable gate arrays, FPGA'10

作者： Zhang, Jiyu Zhang, Zhiru Zhou, Sheng Tan, Mingxing Liu, Xianhua Cheng, Xu Cong, Jason MicroProcessor Research and Development Center Peking University Beijing China Computer Science Department University of California Los Angeles CA 90095 United States PKU/UCLA Joint Research Institute in Science and Engineering China AutoESL Design Technologies Los Angeles CA 90064 United States

ISBN: (纸本)9781605589114

Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level programming languages, such as C/C++, the description of bitwise access and computation is not as direct as hardware description languages, and high-level synthesis of algorithmic descriptions may generate suboptimal implementations for bitwise computation-intensive applications. In this paper we introduce a bit-level transformation and optimization approach to assisting high-level synthesis of algorithmic descriptions. We introduce a bit-flow graph to capture bit-value information. Analysis and optimizing transformations can be performed on this representation, and the optimized results are transformed back to the standard data-flow graphs extended with a few instructions representing bitwise access. this allows high-level synthesis tools to automatically generate circuits with higher quality. Experiments show that our algorithm can reduce slice usage by 29.8% on average for a set of real-life benchmarks on Xilinx Virtex-4 FPGAs. In the meantime, the clock period is reduced by 13.6% on average, with an 11.4% latency reduction. Copyright 2010 acm.

关键词： field programmable gate arrays (FPGA)

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Fast module mapping and placement for datapaths in FPGAs 98

Fast module mapping and placement for datapaths in FPGAs

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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Callahan, Timothy J. Chong, Philip DeHon, Andre Wawrzynek, John Univ of California at Berkeley Berkeley CA United States

ISBN: (纸本)9780897919784

By tailoring a compiler tree-parsing tool for datapath module mapping, we produce good quality results for datapath synthesis in very fast run time. Rather than flattening the design to gates, we preserve the datapath structure;this allows exploitation of specialized datapath features in FPGAs, retains regularity, and also results in a smaller problem size. To further achieve high mapping speed, we formulate the problem as tree covering and solve it efficiently with a linear-time dynamic programming algorithm. In a novel extension to the tree-covering algorithm, we perform module placement simultaneously with the mapping, still in linear time. Integrating placement has the potential to increase the quality of the result since we can optimize total delay including routing delays. To our knowledge this is the first effort to leverage a grammar-based tree covering tool for datapath module mapping. Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity.

关键词： field programmable gate arrays

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the case for registered routing switches in field programmable gate arrays 01

The case for registered routing switches in field programmab...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Singh, D.P. Brown, S.D. Department of Electrical Engineering University of Toronto Toronto Ont. Canada

ISBN: (纸本)9781581133417

FPGAs are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, it has also become a significant bottleneck for high-speed circuits. Even if there are only a few signal paths that run along long stretches of interconnect, it is these paths that may determine the maximum operating frequency of the circuit. In this paper we investigate architectural features that could allow us to automatically pipeline the delay associated with long routes without an excessive area penalty. the goal is to reschedule circuit operations in such a way that a signal may use multiple clock cycles to traverse a long route, rather than requiring a single long clock period. this rescheduling would not effect the timing of the visible outputs (no latency is added to the overall system). Specifically, we analyze the effects of adding a small number of registered routing switches to an FPGA architecture with segmented routing resources. A parameterized FPGA architecture is studied where the percentage of registered routing switches is varied and the speed improvement and area penalty is evaluated. Novel algorithms are presented that allow a circuit to best utilize an architecture with a given percentage of registered switches. We believe that this is the first study that attempts to evauate the tradeoffs associated with switches required in FPGA architectures. Our experiments indicate that the architectural features introduced can produce significant speedup for high speed circuits without excessive area costs. We believe that these techniques will become increasingly important in the future as deep sub-micron process technologies shrink, and wire delays become even more significant.

关键词： field programmable gate arrays

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High-energy physics on DECPeRLe-1 programmable active memory

High-energy physics on DECPeRLe-1 programmable active memory

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Proceedings of the 1995 acm 3rd international symposium on field-programmable gate arrays

作者： Moll, Laurent Vuillemin, Jean Boucard, Philippe Ecole Nationale Superieure des Telecommunications Paris France

the future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DEC-PRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1 [2]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm [3]. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.

关键词： PROM

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Detailed routing architectures for embedded programmable logic IP cores 01

Detailed routing architectures for embedded programmable log...

引用

2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Hallschmid, P. Wilton, S.J.E. Department of Electrical Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781581133417

As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. this ability can be realized using programmable logic cores. these cores are blocks of programmable logic that can be embedded into a fixed-function ASIC or a custom chip. Such cores differ from stand-alone FPGAs in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing characteristics of rectangular programmable logic cores. We quantify the effects of having different x and y channel capacities, and show that the optimum ratio between the x and y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Compared to a simple extension of an existing switch block, our new architecture leads to an 8.7% improvement in density with little effect on speed. Finally, we show that if the channel widths and switch block are chosen carefully the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small;for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 1.1%.

关键词： Application specific integrated circuits

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High-performance, energy-efficient platforms in-socket FPGA accelerators

High-performance, energy-efficient platforms in-socket FPGA ...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Ling, Liu Oliver, Neal Bhushan, Chitlur Qigang, Wang Chen, Alvin Wenbo, Shen Zhihong, Yu Sheiman, Arthur McCallum, Ian Grecco, Joseph Mitchel, Henry Dong, Liu Gupta, Prabhat Intel Corporation

ISBN: (纸本)9781605584102

Growing demand for energy-efficient, high-performance systems has resulted in the growth of innovative heterogeneous computing system architectures that use FPGAs. FPGA-based architectures enable designers to implement custom instruction streams executing on potentially thousands of compute elements. Traditionally, FPGAs have been used as compute elements on PCI devices;however, this does not allow the FPGAs to be coprocessors. this paper describes a high-performance system architecture that is based on the Intel Xeon platform in which one or more FPGAs, acting as application accelerators, replace one or more processors in a dual/multi-processor (DP/MP) platform. the FPGA is thus connected directly to the Front Side Bus (FSB) and enjoys the same privileges as a processor, i.e., full participation in the coherency protocol, unrestricted access to system memory and to other processors via the high bandwidth, and low latency connection to the FSB. In addition, we also describe a software layer called the "Accelerator Abstraction Layer (AAL)", which provides a uniform, hardware- and/or platform-independent application interface. Applications written on AAL can be ported to multiple platforms that have different types of accelerators and the application does not have to be modified. In addition, the AAL also enables the developer/user to reprogram the FPGA on the fly (analogous to an operating system context switch) thereby utilizing the programmable nature of the FPGA. the resulting hardware/software stack creates a flexible and powerful platform for accelerator innovation and deployment. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Reprogrammable network packet processing on the field programmable Port Extender (FPX) 01

Reprogrammable network packet processing on the Field Progra...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Lockwood, J.W. Naufel, N. Turner, J.S. Taylor, D.E. Department of Computer Science Applied Research Lab. Washington University 1 Brookings Drive Saint Louis MO 63130 United States

ISBN: (纸本)9781581133417

A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. this system, the field programmable Port Extender (FPX), enables packet processing functions to be implemented as modular components in reprogrammable hardware. All logic on the on the FPX is implemented in two field programmable gate arrays (FPGAs). Packet processing functions in the system are implemented as dynamically-loadable modules. Core functionality of the FPX is implemented on an FPGA called the Networking Interface Device (NID). the NID contains the logic to transmit and receive packets over a network, dynamically reprogram hardware modules, and route individual traffic flows. A full, non-blocking, switch is implemented on the NID to route packets between the networking interfaces and the modular components. Modular components of the FPX are implemented on a second FPGA called the Reprogrammable Application Device (RAD). Modules are loaded onto the RAD via reconfiguration and/or partial partial reconfiguration of the FPGA. through the combination of the NID and the RAD, the FPX can individually reconfigure the packet processing functionality for one set of traffic flows, while the rest of the system continues to operate. the platform simplifies the development and deployment of new hardware-accelerated packet processing circuits. the modular nature of the system allows an active router to migrate functionality from softare plugins to hardware modules.

关键词： Packet networks

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