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Accelerating SSSP for Power-Law Graphs 22

Accelerating SSSP for Power-Law Graphs

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2022 acm/sigda international symposium on field-programmable gate arrays, FPGA 2022

作者： Chi, Yuze Guo, Licheng Cong, Jason University of California Los Angeles Los AngelesCA United States

ISBN: (纸本)9781450391498

the single-source shortest path (SSSP) problem is one of the most important and well-studied graph problems widely used in many application domains, such as road navigation, neural image reconstruction, and social network analysis. Although we have known various SSSP algorithms for decades, implementing one for large-scale power-law graphs efficiently is still highly challenging today, because - a work-efficient SSSP algorithm requires priority-order traversal of graph data, - the priority queue needs to be scalable both in throughput and capacity, and - priority-order traversal requires extensive random memory accesses on graph data. In this paper, we present SPLAG to accelerate SSSP for power-law graphs on FPGAs. SPLAG uses a coarse-grained priority queue (CGPQ) to enable high-throughput priority-order graph traversal with a large frontier. To mitigate the high-volume random accesses, SPLAG employs a customized vertex cache (CVC) to reduce off-chip memory access and improve the throughput to read and update vertex data. Experimental results on various synthetic and real-world datasets show up to a 4.9× speedup over state-of-the-art SSSP accelerators, a 2.6× speedup over 32-thread CPU running at 4.4 GHz, and a 0.9× speedup over an A100 GPU that has 4.1× power budget and 3.4× HBM bandwidth. Such a high performance would place SPLAG in the 14th position of the Graph 500 benchmark for data intensive applications (the highest using a single FPGA) with only a 45 W power budget. SPLAG is written in high-level synthesis C++ and is fully parameterized, which means it can be easily ported to various different FPGAs with different configurations. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT 24

Quality-driven Design Methodology for PUFs in FPGAs for Secu...

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24th international symposium on Quality Electronic Design (ISQED)

作者： Wang, Xiangyun Song, Yicheng Prakash, Katyayani Zilic, Zeljko Langsetmo, Tomas McGill Univ Montreal PQ Canada KNOX Ind Inc Montreal PQ Canada

ISBN: (纸本)9798350334753

the emergence of Internet of things (IoT) has placed strong emphasis on security. Physical Unclonable Functions (PUFs) are a promising low-cost security solution for IoT. Since field-programmable gate arrays (FPGAs) are more trusted than custom Integrated Circuits (ICs) in building secure systems, implementing PUFs in FPGAs is appealing. In this paper, we propose a methodology for improving the quality of delay-based PUFs on FPGAs. With our method, an asymmetric delay-based PUF has been predictably designed for temperature- and aging-independent operation. Furthermore, the resistance to modeling attacks is built into the design.

关键词： Physical Unclonable Function (PUF) Internet-of-things (IoT) field-programmable gate Array (FPGA) Hardware Security Design Methodology

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Haptic Rendering of Deformable Objects Using a Multiple FPGA Parallel Computing Architecture 10

Haptic Rendering of Deformable Objects Using a Multiple FPGA...

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18th acm international symposium on field-programmable gate arrays

作者： Mandavikhah, Behzad Mafi, Ramin Sirouspour, Shahin Nicolici, Nicola McMaster Univ Hamilton ON Canada

ISBN: (纸本)9781605589114

High-fidelity simulations of haptic interaction with deformable objects is computationally challenging. In this paper, hardware-based parallel computing is proposed for finite-element (FE) analysis of soft-object deformation models. A distributed implementation of the Preconditioned Conjugate Gradient (PCG) algorithms on N field programmable gate Array (FPGA) devices can solve the large system of equations arising from FE models at high update rates required for stable haptic interaction. Massive parallelization of the computations is achieved by customizing the hardware architecture to the problem at hand and concurrently employing a large number of adaptive fixed-point computing units. An implementation of this scalable hardware accelerator on four Altera EP3SE110 FPGA devices is capable of performing 230.4 Giga Operations per second in Sparse Matrix by Vector (SpMxV) multiplication. this architecture has successfully enabled real-time simulation of haptic interaction with a 3-dimensional FE model of 6000 nodes at an update rate of 200 Hz. Both static and dynamic linear elastic models have been successfully simulated.

关键词： field-programmable gate array (FPGA) Finite-element method (FEM) Conjugate Gradient (CG) Soft-object deformation

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Evaluation of the streams-C C-to-FPGA compiler: An applications perspective 01

Evaluation of the streams-C C-to-FPGA compiler: An applicati...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Frigo, J. Gokhale, M. Lavenier, D. Los Alamos National Laboratory Los Alamos NM 87545 United States

ISBN: (纸本)9781581133417

the Streams-C compiler ([5]) synthesizes hardware circuits for reconfigurable FPGA-based computers from parallel C programs. the Streams-C language consists of a small number of libraries and intrinsic functions added to a synthesizable subset of C, and supports a communicating process programming model. the processes may be either software or hardware processes, and the compiler manages communication among the processes transparently to the programmer. For the hardware processes, the compiler generates Register-Transfer-Level (RTL) VHDL, targeting multiple FPGAs with dedicated memories. For the software processes, a multi-threaded software program is generated. the Streams-C language and compiler offer a very high level of expressivity for reconfigurable computing application development, particularly for stream-processing applications. We find this is reflected in productivity, for a factor of up to 10 times improvement in time to produce a program. However, use of the tool in the "real world" is predicated on performance: only if such a compiler can deliver performance comparalble to hand-coded performance will it be used in practice. this paper presents an application study of the Streams-C compiler. Four applications have been written in Streams-C and compiled to the AMC Wildforce board containing Xilinx 4036's. those same applications have been hand-coded in a combination of RTL and structural VHDL. We compare performance of the generated code with the hand-optimized code. Our study shows that the compiler-generated designs are 1.37-4 times the area and 1/2-1 times the clock frequency of the hand designs. We find that the compiler, based on the SUIF infrastructure, can be greatly improved through various standard compiler optimizations that are not currently being exploited. thus we are currently rewriting a public domain version of Streams-C to better optimize and target the Virtex chip.

关键词： field programmable gate arrays

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Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Analysis of the effect of LUT size on FPGA area and delay us...

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6th international symposium on Quality Electronic Design

作者： Gao, HX Yang, YT Ma, XH Dong, G Xidian Univ Microelect Inst Xian 710071 Peoples R China

ISBN: (纸本)0769523013

Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. the effect of LUT size on FPGA area and performance is studied. Results show optimal L UT size conclusion from computation models is same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.

关键词： field programmable gate arrays (FPGA)

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Intel atom processor core made FPGA-synthesizable

Intel atom processor core made FPGA-synthesizable

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Wang, Perry H. Collins, Jamison D. Weaver, Chris T. Kuttanna, Belliappa Salamian, Shahram Chinya, Gautham N. Schuchman, Ethan Schilling, Oliver Doil, thorsten Steibl, Sebastian Wang, Hong Microarchitecture Research Lab Corporate Technology Group Intel Corporation Atom Processor Architecture Mobility Group Intel Corporation Germany Microprocessor Lab Corporate Technology Group Intel Corporation Germany

ISBN: (纸本)9781605584102

We present an FPGA-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transformed and mapped latches in the design, converted clock gating, and replaced nonsynthesizable constructs with FPGA-synthesizable counterparts. Additionally, as the target FPGA emulator is hosted on a PC platform with the Pentium-based CPU socket that supports a significantly different front side bus (FSB) protocol from that of the Atom processor, we replaced the existing bus control logic in the Atom core with an alternate FSB protocol to communicate with the rest of the PC platform. With these efforts, we succeeded in synthesizing the entire Atom processor core to fit within a single Virtex-5 LX330 FPGA. the synthesizable Atom core runs at 50Mhz on the Pentium PC motherboard with fully functional I/O peripherals. It is capable of booting off-the-shelf MS-DOS, Windows XP and Linux operating systems, and executing standard x86 workloads. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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An accurate evaluation of routing density for symmetrical FPGAs 01

An accurate evaluation of routing density for symmetrical FP...

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11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001)

作者： Eum, N.-W. Kim, T. Kyung, C.-M. Electron./Telecom. Res. Institute Taejon Korea Republic of

ISBN: (纸本)9781581133516

this paper presents a scheme for measuring accurate routing density for symmetrical array based field-programmable gate arrays (FPGAs). Unlike the previous routing algorithm in which the estimation of routing density were too general for symmetrical FPGA, we propose new routing density metrics which are tightly linked to the connection topology and the sharing property of routing resources. We then propose a new routing algorithm which uses the density metrics fully and effectively. Experimental results are provided to show the effectiveness of the proposed density metrics on the quality of routing results in terms of performance and routability. In summary, our routing algorithm uses on average 31.9% shorter delay of the longest path even with 6.3% less number of tracks over the results by TRACER-fpga_PR.

关键词： field programmable gate arrays

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Minimizing FPGA reconfiguration data at logic level 06

Minimizing FPGA reconfiguration data at logic level

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7th international symposium on Quality Electronic Design

作者： Raghuraman, Krishna Wang, Haibo Tragoudas, Spyros So Illinois Univ Carbondale IL 62901 USA

ISBN: (纸本)0769525237

A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. three techniques, variable mapping optimization, circuit don't-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. the method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented.

关键词： field programmable gate arrays Reconfigurable logic Table lookup Hardware Circuits Design automation Partitioning algorithms Routing Cost function Scheduling

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Full-system chip multiprocessor power evaluations using FPGA-based emulation

Full-system chip multiprocessor power evaluations using FPGA...

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ISLPED'08: 13th acm/IEEE international symposium on Low Power Electronics and Design

作者： Bhattacharjee, Abhishek Contreras, Gilberto Martonosi, Margaret Department of Electrical Engineering Princeton University

ISBN: (纸本)9781605581095

the design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS, Activity counters programmed into the cores feed per-component microarchitectural power models. these models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35 X speedup compared to full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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the Impact of Interconnect Architecture on Via-Programmed Structured ASICs (VPSAs) 10

The Impact of Interconnect Architecture on Via-Programmed St...

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18th acm international symposium on field-programmable gate arrays

作者： Ahmed, Usman Lemieux, Guy G. F. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781605589114

In this paper, we evaluate the performance of an FPGA-like interconnect fabric for structured ASICs which is based upon fixed metal and programmable vias. We call this type of device a via-programmed structured ASIC or VPSA. We look at two different types of VPSA routing fabrics: one uses jumper wiring and the other uses crossover wiring. the performance of these fabrics is compared against an ASIC-like interconnect fabric, otherwise known as a metal-programmed structured ASIC or MPSA, which can be configured by customizing metal and via layers. We study the impact of these routing fabrics on cost, area, power and delay metrics. the results for different fabrics span a wide range, suggesting the routing architecture plays a very important role in their overall performance and it should be thoroughly researched.

关键词： Structured ASICs Via programmable Fabric

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