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13th international symposium on System Synthesis (ISSS 2000)

作者： Gadea, R Cerdá, J Ballester, F Mocholí, A Univ Politecn Valencia Dept Elect Engn Valencia 46022 Spain

ISBN: (纸本)0769507662

the paper describes the implementation of a systolic array for a multilayer perceptron on a Virtex XCV400 FPGA with a hardware-friendly learning algorithm. A pipelined adaptation of the on-line backpropagation algorithm is shown. Parallelism is better exploited because both forward and backward phases can be performed simultaneously. We can implement very large interconnection layers by using large Xilinx devices with embedded memories alongside the projection used in the systolic architecture. these physical and architectural features - together with the combination of FPGA reconfiguration properties with a design flow based on generic VHDL - create an easy, flexible, and fast method of designing a complete ANN on a single FPGA. the result offers a high degree of parallelism and fast performance.

关键词： Arithmetic Artificial neural networks Backpropagation algorithms field programmable gate arrays Logic arrays Logic devices Neural networks Neurons Signal processing algorithms Systolic arrays

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FPGA Power Reduction by Guarded Evaluation 10

FPGA Power Reduction by Guarded Evaluation

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18th acm international symposium on field-programmable gate arrays

作者： Anderson, Jason H. Ravishankar, Chirag Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781605589114

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. the concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs;in this paper, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. the primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering "non-inverting paths" in the circuit's AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by 22%, on average, and can reduce power consumption in the FPGA interconnect by 14%.

关键词： field-programmable gate arrays FPGAs power optimization low-power design logic synthesis technology mapping

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A Complete Power Estimation Methodology for DSP Blocks in FPGAs

A Complete Power Estimation Methodology for DSP Blocks in FP...

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13th international symposium on Quality Electronic Design (ISQED)

作者： Hassan, Hassan Abdallah, Nizar Microsemi Corp SOC Prod Grp Mountain View CA 94043 USA

ISBN: (纸本)9781467310369;9781467310352

this work proposes a complete commercial power model for DSP blocks in FPGAs. A pin activities model is developed to estimate the transitions densities at the output of the DSP blocks given the switching activities at the inputs. Such a pin activities model is important in estimating power dissipation during the pre-layout design phase. the power model estimates the total power dissipation in the DSP blocks using the knowledge of all the transitions densities of the inputs and outputs, which are estimated by the proposed pin activities model. the average error of the proposed power model on the design level is less than 2%.

关键词： powered models Digital signal processing Desmoplakin Gene power estimation Power dissipation PIN Bone Nails field programmable gate arrays

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Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs 06

Analysis and experimental results of an FPGA-based strategy ...

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7th international symposium on Quality Electronic Design

作者： De Venuto, Daniela Reyneri, Leonardo Politecn Bari Bari Italy Politecn Torino Turin Italy

ISBN: (纸本)0769525237

this work describes an intensive investigation on the test strategy known as polynomial fitting that uses FPGA generated stimuli for cheap and fast testing of high resolution ADCs. Simulation and experimental results showed a sensitivity on the specifications parameters detection of 90dB. the proposed method can also help to control the cost of ADC production test, extends the test coverage and enable built-in self-test and test-based self-calibration.

关键词： Production Circuit testing Automatic testing Polynomials Built-in self-test Signal generators Linearity Histograms Performance evaluation field programmable gate arrays

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Design of a Single Event Upset (SEU) mitigation technique for programmable devices 06

Design of a Single Event Upset (SEU) mitigation technique fo...

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7th international symposium on Quality Electronic Design

作者： Baloch, S. Arslan, T. Stoica, A. Alba Centre Inst Syst Level Integrat Alba Campus Livingston EH54 7EG Scotland Univ Edinburgh Sch Elect & Engg Edinburgh EH8 9YL Midlothian Scotland NASA Jet Propuls Lab Pasadena CA 91109 USA

ISBN: (纸本)0769525237

this paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmable devices. the design technique addresses both conventional static SEUs and SETs (Single Event Transients) induced errors that can result in data loss for reconfigurable architectures. the proposed scheme not only eliminates all SEUs and SETs and but also all double event upsets as well. this approach permits FPGAs and other microcircuits with deep submicron feature size to be used in space environments. the result are included to show that the proposed scheme is over 40% area efficient than previously introduced schemes.

关键词： Single event upset field programmable gate arrays Circuits Microelectronics Random access memory NASA Reconfigurable architectures Ionizing radiation programmable logic arrays Latches

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A 3D-Audio Reconfigurable Processor 10

A 3D-Audio Reconfigurable Processor

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18th acm international symposium on field-programmable gate arrays

作者： theodoropoulos, Dimitris Kuzmanov, Georgi Gaydadjiev, Georgi Delft Univ Technol Dept Elect Engn Comp Engn Lab NL-2600 GA Delft Netherlands

ISBN: (纸本)9781605589114

Various multimedia communication systems based on 3D-Audio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in the literature follow a PC-based approach that introduces processing bottlenecks and excessive power consumption. In order to alleviate these problems, we propose a reconfigurable 3D-Audio processor that can record and render sound sources concurrently. Audio recording and rendering are performed by two hardware accelerators exploiting the beamforming and the Wave field Synthesis algorithms. the theoretical scalability of the proposed processor is explored with respect to systems consisting of different microphone and loudspeaker arrays configurations. A working FPGA prototype is compared against a software implementation on a Core2 Duo system. Results suggest that the proposed reconfigurable hardware solution can process data up to 2.4x faster than the software approach, while power consumption is approximately 7 Watts according to the Xilinx XPower report.

关键词： 3D-Audio Wave field Synthesis Beamforming Reconfigurable Computing Communication Systems

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Circuit partitioning for dynamically reconfigurable FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 187-194页

作者： Liu, Huiqun Wong, D.F. Univ of Texas at Austin Austin TX United States

Dynamically reconfigurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. this paper presents a network-flow based partitioning algorithm for dynamically reconfigurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.

关键词： field programmable gate arrays

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FPGA Acceleration of Short Read Alignment 21

FPGA Acceleration of Short Read Alignment

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11th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021

作者： Koliogeorgi, Konstantina Xydis, Sotirios Soudris, Dimitrios Microprocessors and Digital Systems Laboratory Ece Ntua Greece Harokopio University of Athens Greece

ISBN: (纸本)9781450385497

this work proposes a novel dataflow architecture for Smith-Waterman Matrix-fill and Traceback stages, which are at the heart of short-read alignment on NGS data. the FPGA accelerator is coupled with radical software restructuring to widely-used Bowtie2 aligner to deliver end-to-end speedup while preserving accuracy. © 2021 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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Design for testability of FPGA blocks

Design for testability of FPGA blocks

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5th international symposium on Quality Electronic Design

作者： McCracken, S Zilic, Z Analog Devices Inc Norwood MA 02062 USA

ISBN: (纸本)0769520936

Reconfigurable logic devices that are based on an FPGA substrate are gaining widespread acceptance. As such devices are used in many different configurations, manufacturers need to ensure that each potential configuration will not fail due to device defects. this flexibility leads to severely increased test time. We show how to use reconfigurability to speed up test and diagnosis times of individual FPGA blocks. We present a scheme to incorporate our test architecture, reducing diagnostic and test times of individual FPGA blocks. the test architecture includes added Feedback Shift Registers (FSRs) that change the circuit configuration during test. Algorithms are presented to produce test and diagnosis test sets with a minimized number of test configurations, along with the creation of an FSR that produces the test and diagnosis sets by dynamic reconfiguration of the device.

关键词： field programmable gate arrays

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FPGA-based hardware implementation of generalized profile search using online arithmetic

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 101-110页

作者： Mosanya, Emeka Sanchez, Eduardo Swiss Federal Inst of Technology Lausanne Switzerland

this paper describes the hardware implementation of the Generalized Profile Search algorithm using online arithmetic and redundant data representation. this is part of the GenStorm project, aimed at providing a dedicated computer for biological sequence processing based on reconfigurable hardware using FPGAs. the serial evaluation of the result made possible by a redundant data representation leads to a significant increase of data throughput in comparison with standard non redundant data coding.

关键词： field programmable gate arrays

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