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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Baumela, thomas Gruber, Olivier Muller, Olivier Pétrot, Frédéric Univ. Grenoble Alpes CNRS Grenoble Institute of Engineering TIMA Grenoble38000 France

ISBN: (纸本)9781538675571

Embedded systems increasingly include an FPGA for performance or power efficiency. Fortunately, FPGA makers provide efficient tools to develop and assemble multiple Intellectual Properties (IPs) as devices on FPGAs. Unfortunately, the integration challenge does not stop there, hardware devices are only usable if they have available software device drivers executing on the processor subsystem. To better approach this end-to-end integration challenge, across both hardware and software, we argue that both sides need to evolve. We propose to take a step towards message-based interfaces for hardware devices integrated on an FPGA. Our goal is to deliver to the FPGA market the plug-and-play value of the USB stack with essentially no performance overhead, negligible power increase, and a reasonable surface cost. We have implemented our proposal on the Xilinx Zynq SoC, combining ARM cores and an FPGA, demonstrating the feasibility of the approach. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Configuration caching vs data caching for striped FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 206-214页

作者： Deshpande, Deepali Somani, Arun K. Tyagi, Akhilesh Iowa State Univ Ames IA United States

Striped FPGA, or pipeline-reconfigurable FPGA provides hardware virtualization by supporting fast run-time reconfiguration. In this paper we show that the performance of striped FPGA depends on the reconfiguration pattern, the run time scheduling of configurations through the FPGA. We study two main configuration scheduling approaches- Configuration Caching and Data Caching. We present the quantitative analysis of these scheduling techniques to compute their total execution cycles taking into account the overhead caused by the IO with the external memory. Based on the analysis we can determine which scheduling technique works better for the given application and for the given hardware parameters.

关键词： field programmable gate arrays

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3D-NonFAR: three-dimensional non-volatile FPGA architecture using phase change memory 10

3D-NonFAR: Three-dimensional non-volatile FPGA architecture ...

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Proceedings of the 16th acm/IEEE international symposium on Low power electronics and design

作者： Chen, Yibo Zhao, Jishen Xie, Yuan Department of Computer Science and Engineering Pennsylvania State University University Park PA 16802 United States

ISBN: (纸本)9781450301466

Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero boot-up delay, real-time reconfigurability, and superior energy efficiency. this paper presents a novel threedimensional (3D) non-volatile FPGA architecture (3D-Non- FAR) using phase change memory (PCM) and 3D die stacking techniques. Basic structures in a conventional FPGA architecture are renovated with PCM, and components are repartitioned and reorganized in 3D-NonFAR to allow an efficient 3D integration of PCM elements. 3D-NonFAR not only preserves the advantages of existing non-volatile FPGAs, but also provides high integration density, high performance, and bit-level programmability, which enable PCM as a universal memory replacement in FPGAs. Evaluation results show that 3D-NonFAR has smaller footprint, higher performance, and lower power consumption compared with other FPGA counterparts. Copyright 2010 acm.

关键词： field programmable gate arrays (FPGA)

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Synthesis of Custom Networks of Heterogeneous Processing Elements for Complex Physical System Emulation 12

Synthesis of Custom Networks of Heterogeneous Processing Ele...

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10th acm international Conference on Hardware/Software-Codesign and System Synthesis

作者： Huang, Chen Miller, Bailey Vahid, Frank Givargis, Tony Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA USA

ISBN: (纸本)9781450314268

Physical system models that consist of thousands of ordinary differential equations can be synthesized to field-programmable gate arrays (FPGAs) for highly-parallelized, real-time physical system emulation. Previous work introduced synthesis of custom networks of homogeneous processing elements, consisting of processing elements that are either all general differential equation solvers or are all custom solvers tailored to solve specific equations. However, a complex physical system model may contain different types of equations such that using only general solvers or only custom solvers does not provide all of the possible speedup. We introduce methods to synthesize a custom network of heterogeneous processing elements for emulating physical systems, where each element is either a general or custom differential equation solver. We show average speedups of 45x over a 3 GHz single-core desktop processor, and of 11x and 20x over a 3 GHz four-core desktop and a 763 MHz NVIDIA graphical processing unit, respectively. Compared to a commercial high-level synthesis tool including regularity extraction, the networks of heterogeneous processing elements were on average 10.8x faster. Compared to homogeneous networks of general and single-type custom processing elements, heterogeneous networks were on average 7x and 6x faster, respectively.

关键词： Real-time emulation field-programmable gate array (FPGA) ordinary differential equation (ODE) solving physical models cyber-physical systems differential equation synthesis high-level synthesis system-level synthesis processing elements

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Exploiting FPGA-features during the emulation of a fast reactive embedded system

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 235-242页

作者： Weiss, Karlheinz Steckstor, thorsten Koch, Gernot Rasenstiel, Wolfgang Univ of Tuebingen Tuebingen Germany

this paper presents the emulation of an embedded system with hard real time constraints and response times of about 220 μs. We show that for such fast reactive systems, the software overhead of a Real Time Operating System (RTOS) becomes a limiting factor, consuming up to 77% of the total execution performance. We analyze features of different FPGA architectures in order to solve the system performance bottleneck. We show that moving functionality from software to hardware through exploiting the fine grained on-chip SRAM capability of the Xilinx XC4000 architecture, that feature eliminates the RTOS overhead by only a slight increase of about 28% of the used FPGA CLB resources. these investigations have been conducted using our own emulation environment called SPYDER-CORE-P1.

关键词： field programmable gate arrays

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Methodology for fast FPGA floorplanning

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 47-56页

作者： Emmert, John M. Bhatia, Dinesh Univ of Cincinnati Cincinnati United States

Floorplanning is an important problem in FPGA circuit mapping. As FPGA capacity grows, new innovative approaches will be required for efficiently mapping circuits to FPGAs. In this paper we present a macro based floorplanning methodology suitable for mapping large circuits to large, high density FPGAs. Our method uses clustering techniques to combine macros into clusters, and then uses a tabu search based approach to place clusters while enhancing both circuit routability and performance. Our method is capable of handling both hard (fixed size and shape) macros and sob (fixed size and variable shape) macros. We demonstrate our methodology on several macro based circuit designs and compare the execution speed and quality of results with commercially available CAE tools. Our approach shows a dramatic speedup in execution time without any negative impact on quality.

关键词： field programmable gate arrays

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Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models 24

Accounting for Floorplan Irregularity and Configuration Depe...

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24th international symposium on Quality Electronic Design (ISQED)

作者： Barajas, Gabriel Greene, Jonathan W. Li, Fei Tandon, James Microchip San Jose CA 95134 USA Cambios Comp LLC Palo Alto CA USA Calif State Univ East Bay Hayward CA USA

ISBN: (纸本)9798350334753

Accurate delay estimates for a user application implemented in a field-programmable gate Array (FPGA) are essential for a quality FPGA timing flow and to avoid leaving performance on the table. FPGA inter-cluster routing consists of wire segments of a limited number of types which repeat in a somewhat regular pattern, interconnected by configurable muxes. the delay at any fanout of a segment can be significantly impacted by configuration-dependent capacitive loading related to other fanouts. Also, the insertion of RAM and math blocks into the FPGA floorplan introduces irregular stretching of the wire segments, altering their delays. We explain why and how commercial FPGA software typically employs a parameterized model for the delay at each fanout of a segment, based on the configuration and the irregularities present, with the parameters determined by fitting SPICE simulation data for a representative sample of cases. We propose incorporating readily-computed common path resistance values into the model. this enables high accuracy with fewer parameters and without the large amounts of SPICE data that would otherwise be required to explore interactions between floorplan irregularities and the set of active fanouts. In combination with other features of our models, errors in segment delay are reduced by almost half.

关键词： field-programmable gate arrays FPGAs delay estimation Elmore delay common path resistance

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New high density and very low cost reprogrammable FPGA architecture

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 3-12页

作者： Kaptanoglu, Sinan Bakker, Greg Kundu, Arun Corneillet, Ivan Ting, Ben Actel Corp Sunnyvale United States

A new reprogrammable FPGA architecture is described which is specifically designed to be of very low cost. It covers a range of 35 K to a million usable gates. In addition, it delivers high performance and it is synthesis efficient. this architecture is loosely based on an earlier reprogrammable Actel architecture named ES. By changing the structure of the interconnect and by making other improvements, we achieved an average cost reduction by a factor of three per usable gate. the first member of the family based on this architecture is fabricated on a 2.5 V standard 0.25μ CMOS technology with a gate count of up to 130 K which also includes 36 K bits of two port RAM. the gate count of this part is verified in a fully automatic design flow starting from a high level description followed by synthesis, technology mapping, place and route, and timing extraction.

关键词： field programmable gate arrays

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FPGA routing architecture: Segmentation and buffering to optimize speed and density

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 59-68页

作者： Betz, Vaughn Rose, Jonathan Univ of Toronto Toronto Canada

In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transistor and tri-state buffer routing switches. While most commercial FPGAs contain many length 1 wires (wires that span only one logic block) we find that wires this short lead to FPGAs that are inferior in terms of both delay and routing area. Our results show instead that it is best for FPGA routing segments to have lengths of 4 to 8 logic blocks. We also show that 50% to 80% of the routing switches in an FPGA should be pass transistors, with the remainder being tri-state buffers. Architectures that employ the best segmentation distributions and the best mixes of pass transistor and tri-state buffer switches found in this paper are not only 11% to 18% faster than a routing architecture very similar to that of the Xilinx XC4000X but also considerably simpler. these results are obtained using an architecture investigation infrastructure that contains a fully timing-driven router and detailed area and delay models.

关键词： field programmable gate arrays

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FPIA: field-programmable Ising arrays with In-Memory Computing 24

FPIA: Field-Programmable Ising Arrays with In-Memory Computi...

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29th acm/IEEE international symposium on Low Power Electronics and Design, ISLPED 2024

作者： Hutchinson, George Higgins Sifferman, Ethan Bhattacharya, Tinish Kwon, Dongseok Strukov, Dmitri B Department of Electrical and Computer Engineering University of California at Santa Barbara Santa BarbaraCA United States

ISBN: (纸本)9798400706882

Ising Machines, a promising approach for solving combinatorial optimization problems, are naturally suited for energy-saving and compact in-memory computing implementations with emerging memories. A naïve in-memory computing implementation of a quadratic Ising Machine requires an array of coupling weights that grows quadratically with problem size. this approach, however, uses resources inefficiently due to the inherent sparsity of practical optimization problems. We first show that this issue can be addressed by partitioning a coupling array into smaller sub-arrays. this technique, however, requires interconnecting sub-arrays, which incurs overhead. In response, we present FPIA, an in-memory computing architecture for quadratic Ising Machines inspired by island-type field programmable gate arrays. We adapt open-source tools to optimize problem embedding and model overhead. Modeling results of benchmark problems for the developed architecture show up to 10x increase in density and speed compared to the baseline approach. Finally, we discuss algorithm/circuit co-design techniques for further improvements. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to acm.

关键词： Ising model

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