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7th international symposium on Quality Electronic Design

作者： Kumar, Akhilesh Anis, Mohab Univ Waterloo Dept ECE 200 Univ Ave W Waterloo ON N2L 3G1 Canada

ISBN: (纸本)0769525237

In this paper we propose a dual-Vt FPGA architecture for reduction of subthreshold leakage power A CAD flow has been proposed based on the dual-Vt assignment algorithm and placement for realizing the dual-Vt FPGA architecture. Logic elements within the logic blocks are the candidates for dual-Vt assignment. We propose an architecture in which there are two kinds of logic blocks, one with all high-Vt logic elements and another with a fixed percentage of high-Vt logic elements. these two kinds of logic blocks are then placed in such a way that the FPGA architecture remains regular Results indicate that in the ideal case of dual-Vt assignment, over 95% of the logic elements can be assigned high-Vt. Results show that leakage savings of 55% can be achieved. Design tradeoffs for various ratios of the two kinds of logic blocks are investigated. the dual-Vt FPGA CAD flow is intended for development and evaluation of dual-Vt FPGA architectures.

关键词： field programmable gate arrays Subthreshold current Routing Switches Design automation Circuits threshold voltage Logic design Sleep MOS devices

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Embedded supercomputing in FPGAs with the VectorBlox MXP matrix processor

Embedded supercomputing in FPGAs with the VectorBlox MXP mat...

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11th acm/IEEE international Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013

作者： Severance, Aaron Lemieux, Guy G.F. University of British Columbia VectorBlox Computing Inc. Canada

ISBN: (纸本)9781479914173

Embedded systems frequently use FPGAs to perform highly parallel data processing tasks. However, building such a system usually requires specialized hardware design skills with VHDL or Verilog. Instead, this paper presents the VectorBlox MXP Matrix Processor, an FPGA-based soft processor capable of highly parallel execution. Programmed entirely in C, the MXP is capable of executing data-parallel software algorithms at hardware-like speeds. For example, the MXP running at 200MHz or higher can implement a multi-tap FIR filter and output 1 element per clock cycle. MXP's parameterized design lets the user specify the amount of parallelism required, ranging from 1 to 128 or more parallel ALUs. Key features of the MXP include a parallel-access scratchpad memory to hold vector data and high-throughput DMA and scatter/gather engines. To provide extreme performance, the processor is expandable with custom vector instructions and custom DMA filters. Finally, the MXP seamlessly ties into existing Altera and Xilinx development flows, simplifying system creation and deployment. © 2013 IEEE.

关键词： field programmable gate arrays (FPGA)

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Multi-terminal net routing for partial crossbar-based multi-FPGA systems

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 176-184页

作者： Ejnioui, Abdel Ranganathan, N. Univ of South Florida Tampa FL United States

Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multi-terminal nets in a multi-FPGA system that uses partial crossbars as interconnect structures. First, we model the multi-terminal routing problem as a partitioned bin packing problem and formulate it as an integer linear programming problem where the number of variables is exponential. A fast heuristic is applied to compute an upper bound on the routing solution. then, a column generation technique is used to solve the linear relaxation of the initial master problem in order to obtain a lower bound on the routing solution. this is followed by an iterative branch-and-price procedure that attempts to find a routing solution somewhere between the two established bounds. In this regard, the proposed algorithm guarantees an exact routing solution by searching a branch-and-price tree. Due to the tightness of the bounds, the branch-and-price tree is small resulting in shorter execution times. Experimental results are provided for different netlists and board configurations in order to demonstrate the algorithm's performance. the obtained results show that the algorithm finds an exact routing solution in a very short time.

关键词： field programmable gate arrays

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Simulation-based circuit-activity estimation for FPGAs containing hard blocks 28

Simulation-based circuit-activity estimation for FPGAs conta...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Seeley, Sean Sankaranaryanan, Vidya Deveau, Zack Patros, Panagiotis Kent, Kenneth B. Faculty of Computer Science University of New Brunswick Canada

ISBN: (纸本)9781450354189

FPGAs are electronic devices that are programmable and can functionally perform equivalently to a number of other circuits. FPGAs are used for both rapid and cheap prototyping of new circuit designs as well as for replacing outdated chip models. Due to their complexity, circuits cannot be practically designed by hand;instead, specialized Computer Aided Design (CAD) software performs this complex task. A major concern for devices is power requirements, which can have adverse effects on both the environment and users. the power requirements of a circuit can be directly connected with its activity, which can be estimated by the CAD tools. In this work, we focus on the open source Verilog-To-Routing (VTR) CAD software and propose an improved activity estimation tool using VTR's synthesizer (Odin II) that extends beyond the capabilities of its current estimator (ACE2), such as proper black box activity propagation and support for circuits containing no clocks or more than one clock. Our results are experimentally evaluated with VTR's FPGA architectures and benchmark circuits. © 2017 acm.

关键词： field programmable gate arrays (FPGA)

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Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks 21

Towards Performance Characterization of FPGAs in Context of ...

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11th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021

作者： Meyer, Marius Paderborn Germany

ISBN: (纸本)9781450385497

OpenCL-based HLS frameworks are known to reduce the development effort for FPGAs while offering good quality results. the upcoming trend to equip heterogeneous compute clusters with hybrid networks for inter-CPU and inter-FPGA communication allows scaling FPGA workloads beyond a single FPGA. However, there is no tool for performance characterization of those FPGA-accelerated systems and their communication networks yet. To fill this gap, we implemented a parametrizable OpenCL benchmark suite for FPGA based on the HPC Challenge for CPU. In the first step, we showed that the parametrization of the benchmarks allows high quality of results on Intel and Xilinx FPGAs. In the future, we plan to extend the benchmarks to scale over multiple FPGAs to create a performance characterization tool for HPC multi-FPGA systems and further investigate the opportunities and limitations of different inter-FPGA communication approaches. © 2021 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate...

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acm/sigda international symposium on field programmable gate arrays - FPGA 1999年 227-234页

作者： Kollig, P. Al-Hashimi, B.M. Staffordshire Univ Stafford United Kingdom

Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications are used. this paper describes a novel methodology for the design of generic bit-level pipelined data paths that have the low resource usage and latency of specifically tailored architectures but still allow the flexible trade-off between speed and resource requirements inherent in generic circuits. this is achieved through the elimination of all skew and alignment flip-flops from the data path whilst still maintaining the original pipelining scheme, hence allowing more compact structures with decreased circuit delays. the resulting low latency is beneficial in the realization of all recursive signal-processing applications and the reduced resource usage enables particularly the efficient FPGA realization of high performance signal processing functions. the design process is illustrated through the high level synthesis-based FPGA realization of a 9th-order wave digital filter, demonstrating that high performance and efficient resource usage are possible. For example, the implementation of a wave digital filter with 10-bit signal word length and 6 bit coefficients using a Xilinx XCA013XL-1 device supports sample rates of 2.5 MHz.

关键词： field programmable gate arrays

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Accelerating Matrix Processing for MIMO Systems 21

Accelerating Matrix Processing for MIMO Systems

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11th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021

作者： Xu, Jieming Leeser, Miriam MathWorks NatickMA United States Northeastern University BostonMA United States

ISBN: (纸本)9781450385497

Massive Multiple In and Multiple Out (MIMO) is being used in the fifth generation of wireless communication systems. As the number of antennas increases, the computational complexity grows dramatically, and this involves matrix calculations with complex numbers. We have designed and implemented a general matrix arithmetic processor to accelerate these calculations, including matrix multiplication, Singular Value Decomposition (SVD), and QR decomposition, on an FPGA. the design can be implemented in fixed-point or single-precision floating-point depending on the requirements of the application. the system behavior can be controlled by instructions such as elementary multiplication, rotation and vector projection, which allows the system to work as a coprocessor in a baseband System on a Chip (SoC). Latency for changing from one matrix computation to another is just a few clock cycles, providing the low latency required for edge processing. the design is implemented and verified on the Xilinx RFSoC development board using fixed point and single precision floating point numbers and matrix sizes of 8 × 8 and 16 × 16. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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Prototyping dynamic task migration on heterogeneous reconfigurable systems 28

Prototyping dynamic task migration on heterogeneous reconfig...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Wicaksana, Arief Bourge, Alban Muller, Olivier Sasongko, Arif Rousseau, Frédéric Univ. Grenoble Alpes TIMA CNRS Grenoble France Institut Teknologi Bandung Bandung Indonesia

ISBN: (纸本)9781450354189

Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. the extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. the proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented. © 2017 acm.

关键词： field programmable gate arrays (FPGA)

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PvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment

PvFPGA: Accessing an FPGA-based hardware accelerator in a pa...

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11th acm/IEEE international Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013

作者： Wang, Wei Bolic, Miodrag Parri, Jonathan Computer Architecture Research Group University of Ottawa Ottawa ON Canada

ISBN: (纸本)9781479914173

In this paper we present pvFPGA, the first system design solution for virtualizing an FPGA-based hardware accelerator on the x86 platform. Our design adopts the Xen virtual machine monitor (VMM) to build a paravirtualized environment, and a Xilinx Virtex-6 as an FPGA accelerator. the accelerator communicates with the x86 server via PCI Express (PCIe). In comparison to the recent accelerator virtualization solutions which primarily intercept and redirect API calls to the hosted or privileged domain's user space, pvFPGA virtualizes an FPGA accelerator directly at the lower device driver level. this gives rise to higher efficiency and lower overhead. In pvFPGA, each unprivileged domain allocates a shared data pool for both user-kernel and inter-domain data transfer. In addition, we propose a new component, the coprovisor, which enables multiple domains to simultaneously access an FPGA accelerator. the experimental results have shown that 1) pvFPGA achieves close-to-zero overhead compared to accessing the FPGA accelerator without the VMM layer, 2) the FPGA accelerator is successfully shared by multiple domains, and 3) distributing different maximum data transfer bandwidths to different domains is achieved by regulating the size of the shared data pool at the split driver loading time. © 2013 IEEE.

关键词： field programmable gate arrays (FPGA)

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PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing 29

PyXEL: An Integrated Environment for the Analysis of Fault E...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Bozzoli, Ludovica De Sio, Corrado Sterpone, Luca Bernardeschi, Cinzia Dipartimento di Automatica e Informatica Politecnico di Torino Torino Italy Department of Information Engineering University of Pisa Pisa Italy

ISBN: (纸本)9781538675571

In the last decades, FPGAs have been increasingly used in many different mission critical applications, such as the avionics and aerospace ones. thus, research interest in studying faults in FPGAs has seen a sharp increase, especially for those applications that require high dependability and must operate in harsh environments. the increase of resources available in FPGA devices has caused a huge growth in routing complexity. Nowadays, more than 80% of transistors in modern FPGAs are related to the routing infrastructure. the analysis of faults related to routing structure of FPGA devices is a hard task due to the lack of tools working at low-level, limited information availability about interconnection structure from vendors and, above all, no automated testing workflow for such kind of resources. In this paper, we introduce PyXEL, an integrated environment realized to automatize the analysis of fault effects in FPGAs routing structure. PyXEL is a Python-based framework that allows to easily manipulate FPGAs bitstreams in order to inject specific faults and to analyze their behavior. Moreover, PyXEL provides an easy way to build and run experimental workflow interacting directly with Xilinx Vivado and ISE allowing to select routing resources to test and logically analyze results. We demonstrated the feasibility and the advantages of our approach exploiting PyXEL to gain insight into the electrical effects of faults in the routing interconnections of the Xilinx Artix-7. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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