In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based fieldprogrammablegatearrays. the algorithm is based on a novel iterative procedure for computing all k-cuts of all...
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In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based fieldprogrammablegatearrays. the algorithm is based on a novel iterative procedure for computing all k-cuts of all nodes in a sequential circuit, in the presence of retiming. the algorithm completely avoids flow computation which is the bottleneck of previous algorithms. Due to the fact that k is very small in practice, the procedure for computing all k-cuts is very fast. Experimental results indicate the overall algorithm is very efficient in practice.
this paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) fieldprogrammablegatearrays (FPGAs). the proposed approach detects bridging faults and is based on quiescent c...
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ISBN:
(纸本)9780897919784
this paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) fieldprogrammablegatearrays (FPGAs). the proposed approach detects bridging faults and is based on quiescent current (IDDQ) monitoring. Compared with previous voltage-based methods, IDDQ testing has the advantage of utilizing a small number of programming phases for configuring the FPGA during the test process with negligible observability requirements, even under multiple faults. Algorithms for test generation which exploit the homogeneous nature of the FPGA array, are described. An example using the XC4000 is described in detail. For testing the XC4000 series interconnect, a total of 20 phases and 11 vectors are required: 11 phases for S (switch) block testing, and 9 phases for C (connection) block testing.
An algorithm is presented for partitioning a design in time. the algorithm divides a large, technology-mapped design into multiple configurations of a time-multiplexed FPGA. these configurations are rapidly executed i...
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ISBN:
(纸本)9780897919784
An algorithm is presented for partitioning a design in time. the algorithm divides a large, technology-mapped design into multiple configurations of a time-multiplexed FPGA. these configurations are rapidly executed in the FPGA to emulate the large design. the tool includes facilities for optimizing the partitioning to improve routability, for fitting the design into more configurations than the depth of the critical path and for compressing the critical path of the design into fewer configurations, both to fit the design into the device and to improve performance. Scheduling results are shown for mapping designs into an 8-configuration time-multiplexed FPGA and for architecture investigation for a time-multiplexed FPGA.
three factors are driving the demand for rapid fieldprogrammablegate array (FPGA) compilation. First, as FPGAs grown in logic capacity, the compile computation grows more quickly than the compute power of the availa...
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three factors are driving the demand for rapid fieldprogrammablegate array (FPGA) compilation. First, as FPGAs grown in logic capacity, the compile computation grows more quickly than the compute power of the available computers. Second, there exists a subset of users who are willing to pay for very high speed compile with a decrease in quality of result. third, very high speed compile is a long-standing desire of those using FPGA-based custom computing machines, as they want compile times at least closer to those of regular computers. A routing algorithm and routing tool that relates these three unique capabilities to very high-speed compile is presented.
this paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. the proposed architecture provides the flexibility of a DSP processor with per...
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this paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. the proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.
Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal withthis overhead, and increase the power of reconfigurable systems, it is im...
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ISBN:
(纸本)9780897919784
Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal withthis overhead, and increase the power of reconfigurable systems, it is important to develop hardware and software systems to reduce or eliminate this delay. In this paper we propose one technique for significantly reducing the reconfiguration latency: the prefetching of configurations. By loading a configuration into the reconfigurable logic in advance of when it is needed, we can overlap the reconfiguration with useful computation. We demonstrate the power of this technique, and propose an algorithm for automatically adding prefetch operations into reconfigurable applications. this results in a significant decrease in the reconfiguration overhead for these applications.
To implement high-density and high-speed FPGA circuits, designers need tight control over the circuit implementation process. However, current design tools are unsuited for this purpose as they lack fast turnaround ti...
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ISBN:
(纸本)9780897919784
To implement high-density and high-speed FPGA circuits, designers need tight control over the circuit implementation process. However, current design tools are unsuited for this purpose as they lack fast turnaround times, interactiveness, and integration. We present a system for the Xilinx XC6200 FPGA, which addresses these issues. It consists of a suite of tightly integrated tools for the XC6200 architecture centered around an architecture-independent tool framework. the system lets the designer easily intervene at various stages of the design process and features design cycle times (from an HDL specification to a complete layout) in the order of seconds.
While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to sign...
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ISBN:
(纸本)9780897919784
While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce boththese costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. the result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2.
Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise ins...
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ISBN:
(纸本)9780897919784
Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area reduction. Once low die cost is achieved, it is seen that testing and packaging costs must be considered. Interactions among these three cost contributors pose trade-offs that prevent independent optimization. this paper discusses solutions discovered by the architects optimizing the Altera FLEX 6000 architecture.
this paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing's H.O.T. Works board) can be exploited to accelerate the time-consuming fitn...
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ISBN:
(纸本)9780897919784
this paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing's H.O.T. Works board) can be exploited to accelerate the time-consuming fitness measurement task of genetic algorithms and genetic programming. this acceleration is accomplished by embodying each individual of the evolving population into hardware in order to perform the fitness measurement task. A 16-step sorting network for seven items was evolved that has two fewer steps than the sorting network described in the 1962 O'Connor and Nelson patent on sorting networks (and the same number of steps as a 7-sorter that was devised by Floyd and Knuth subsequent to the patent and that is now known to be minimal). Other minimal sorters have been evolved.
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