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Implementation of a RISC-V SMT Core in an AI processor 22

Implementation of a RISC-V SMT Core in an AI processor

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11th international symposium on Information and Communication Technology, SoICT 2022

作者： Tanaka, Hidetaro Tanaka, Tomoaki Higashi, Ryosuke Sekibe, Tsutomu Takada, Shuichi Nakajo, Hironori Tokyo University of Agriculture and Technology Tokyo Japan ArchiTek Corporation Osaka Japan

ISBN: (纸本)9781450397254

the RISC-V core, which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture, has been implemented. In the architecture, multiple types of engines specialized for different purposes are included. the RISC-V SMT core has the advantage of allowing multiple threads to execute simultaneously with a lower cost than that of simply using multiple cores. the RISC-V core supports operations of other engines under the SMT mechanism to be installed in "Chichibu,"which has been developed by ArchiTek Co., LTD as a multicore chip for edge artificial intelligence. In this implementation, we have reduced the hardware resource usage to less than half that of the previous implementation and exceeded the operating frequency of 100 MHz. In addition, the instructions per clock cycle (IPC) has been improved by approximately 66% using SMT. © 2022 acm.

关键词： field programmable gate arrays (FPGA)

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Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper 29

Rapid Prototyping of Parameterized Rotated and Cyclic Q Dela...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Waqas, Muhammad Jafri, Atif Raza Baghdadi, Amer Najam-Ul-Islam, M. Bahria University Islamabad Pakistan Lab-STICC laboratory IMT Atlantique Brest France

ISBN: (纸本)9781538675571

Rotated and Cyclic Q Delayed (RCQD) modulation is one of the signal processing schemes which, once used on the transmitter side, provides performance improvement on receiver side in case of fading channel conditions with erasures. However, an efficient hardware solution in terms of low area and high throughput is mandatory to get benefit from this modulation technique. In this paper we have implemented a parameterized hardware architecture of most recent RCQD demapping technique supporting different constellations. In addition to the description of the proposed hardware architecture, rapid prototyping flow based on LabVIEW FPGA is described which is useful to explore different design schemes in short period of time. the implementation results are achieved by FPGA prototyping while targeting NI-USRP RIO hardware equipment. By comparing our rapidly prototyped parameterized RCQD demapper with other state-of-the-art implementation schemes, it is shown that our prototyped demapper consumed lesser hardware resources and achieved higher throughput with very short design time. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Kyokko: A vendor-independent high-speed serial communication controller 21

Kyokko: A vendor-independent high-speed serial communication...

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11th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021

作者： Tomori, Akinobu Osana, Yasunori University of the Ryukyus Okinawa Nishihara Japan

ISBN: (纸本)9781450385497

With the advancement of HLS technology, FPGA is finally drawing attention as a power-efficient accelerator device. Unlike GPUs, the computation pipeline and FPGA-to-FPGA interconnection can be tightly coupled on FPGAs because they have high-speed serial transceivers on the device itself. the direct connection between computation and network encourages building FPGA clusters with direct high-speed serial links between FPGAs. For these links, commercial IP cores with their proprietary protocol are widely used. However, the commercial IP cores and protocols are not fully customizable. In this paper, an open high-speed serial link controller Kyokko is introduced. Kyokko is based on Xilinx Aurora 64B/66B protocol. It achieves 10+ Gbps of link rates with flow control and channel bonding support within a smaller resource requirement and communication latency than Xilinx's Aurora IP core. the transceiver interface of Kyokko is portable and interoperable between both Intel and Xilinx FPGAs. Also, users can extend the protocol to meet their demands because Kyokko is an open-source project. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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Software-like Compilation for Data Center FPGA Accelerators 21

Software-like Compilation for Data Center FPGA Accelerators

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11th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021

作者： thomas, James Lavin, Chris Kaviani, Alireza Stanford University CA United States Xilinx Cto LongmontCO United States

ISBN: (纸本)9781450385497

Compilation times for large Xilinx devices, such as the Amazon F1 instance, are on the order of several hours. However, today's data center designs often have many identical processing units (PUs), meaning that conventional design flows waste time placing and routing the same problem many times. Furthermore, the connectivity infrastructure of a design tends to be finalized before the PUs, resulting in unnecessary recompilation of a large fraction of the design. We present an open source flow where the connectivity infrastructure logic is implemented ahead of time and routed to many interface blocks that border available slots for PUs. As architects iterate on their PU designs, they only need to perform a single set of parallel, independent compile runs to implement and route the PU alongside each distinct interface block. Our RapidWright-based system stitches the implemented PU into the available slots in the connectivity logic, requiring no additional routing to finalize the design. Our system is able to generate working designs for Amazon F1, and reduces compilation time over the standard monolithic compilation flow by an order of magnitude for designs with up to 180 PUs. Our experiments also show that there is future potential for an additional 4X runtime improvement when relying on emerging open source place and route tools. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation 21

Large-scale combinatorial optimization in real-time systems ...

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11th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021

作者： Tatsumura, Kosuke Corporate Research and Development Center Toshiba Corporation Kanagawa Kawasaki Japan

ISBN: (纸本)9781450385497

Combinatorial optimization problems are economically valuable but computationally hard to solve. Many practical combinatorial optimizations can be converted to the ground-state search problems of Ising spin models. Simulated bifurcation (SB) is a quantum-inspired algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism, providing an opportunity for quickly solving those problems by massively parallel processing. In this article, we review our recent works on the design and implementation of high-performance FPGA-based accelerators for SB and their applications toward innovative real-time systems that make optimal responses to ever-changing situations. An example of such an application is an ultrafast financial transaction machine that detects the most profitable cross-currency arbitrage opportunities at microsecond speeds. Also, we show a scale-out architecture for SB-based Ising machines with all-to-all spin-spin couplings that allows continued scaling of both machine size and computational throughput by connecting multiple chips, rather than scaling up a single chip. © 2021 Owner/Author.

关键词： field programmable gate arrays (FPGA)

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Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC 29

Vicilogic 2.0: Online Learning and Prototyping of Digital Sy...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Morgan, Fearghal O'loughlin, Declan Audiger, Jeremy Boyer, Yohan Timlin-Canning, Niall Kepa, Krzysztof Cawley, Seamus Gallivan, Ian Bako, László Callaly, Frank National University of Ireland Galway Ireland Sapientia Hungarian University of Transylvania Romania

ISBN: (纸本)9781538675571

this paper presents viciLogic 2.0, a scalable, distributed online learning, hardware prototyping, client application and course creator platform for System on Chip (SoC)-based digital systems. User applications transparently link to a device in an array of Xilinx PYNQ-Zl or-Z2 SoC hardware in the cloud. the viciLogic prototype builder toolsuite (which integrates with the Xilinx Vivado industry-standard EDA tools) automates online (and local) SoC digital logic hardware prototyping, with integrated viciLogic user interface. the platform supports real-time user hardware input signal control and automated signal control, and probes the state of all user design internal and output signals. this enables the creation of responsive client applications and smart browser-based courses. Online course functions include guided lessons, SoC signal state monitoring for automatic course progression, knowledge checks, and user sandbox. the prototype builder uses source VHDL or Verilog projects created, simulated and synthesised in Vivado. the builder parses and modifies the HDL model to provide signal observability, integrates SoC resources (ARM, AXI interconnect, peripherals and viciLogic IP), and (using Vivado) generates the SoC hardware configuration bitstream and design metadata. the paper describes the viciLogic 2.0 server architecture, SoC prototype builder tool flow, client application creator, and online course creator. Two demonstration applications are presented, a counter course lesson step and a client application (16-bit single cycle computer, with IDE). © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Session details: New directions for programmable devices 05

Session details: New directions for programmable devices

引用

Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Steve Trimberger Xilinx

No abstract available.

ISBN: (纸本)9781595930293

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SEU-Mitigation placement and routing algorithms and their impact in SRAM-based FPGAs

SEU-Mitigation placement and routing algorithms and their im...

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8th international symposium on Quality Electronic Design

作者： Zarandi, Hamid R. Miremadi, Seyed G. Pradhan, Dhiraj K. Mathew, Jimson Sharif Univ Technol Dept Comp Engn Tehran Iran Univ Bristol Dept Comp Sci Bristol Avon England

ISBN: (纸本)9780769527956

In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. the VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. the secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility reductions are cumulative or not when they applied in sequence. We have investigated the effect of S-VPR on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. the evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 18% and 12%, respectively. However, it increases critical path delay and power consumptions of the circuits up to 5% and 8%, respectively. this means that without any redundancies, just by means of fault-avoidance method, mitigation of SEU effects would decrease up to 22% significantly and this method is notable compared to previous TMR and DWC mechanisms.

关键词： field programmable gate arrays (FPGA)

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StreamBrain: An HPC Framework for Brain-like Neural Networks on CPUs, GPUs and FPGAs 21

StreamBrain: An HPC Framework for Brain-like Neural Networks...

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11th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021

作者： Podobas, Artur Svedin, Martin Chien, Steven W. D. Peng, Ivy B. Ravichandran, Naresh Balaji Herman, Pawel Lansner, Anders Markidis, Stefano Kth Royal Institute of Technology Stockholm Sweden

ISBN: (纸本)9781450385497

the modern deep learning method based on backpropagation has surged in popularity and has been used in multiple domains and application areas. At the same time, there are other - less-known - machine learning algorithms with a mature and solid theoretical foundation whose performance remains unexplored. One such example is the brain-like Bayesian Confidence Propagation Neural Network (BCPNN). In this paper, we introduce StreamBrain - a framework that allows neural networks based on BCPNN to be practically deployed in High-Performance Computing systems. StreamBrain is a domain-specific language (DSL), similar in concept to existing machine learning (ML) frameworks, and supports backends for CPUs, GPUs, and even FPGAs. We empirically demonstrate that StreamBrain can train the well-known ML benchmark dataset MNIST within seconds, and we are the first to demonstrate BCPNN on STL-10 size networks. We also show how StreamBrain can be used to train with custom floating-point formats and illustrate the impact of using different bfloat variations on BCPNN using FPGAs. © 2021 acm.

关键词： field programmable gate arrays (FPGA)

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Amplifying embedded system efficiency via automatic instruction fusion on a post-manufacturing reconfigurable architecture platform

Amplifying embedded system efficiency via automatic instruct...

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9th international symposium on Quality Electronic Design

作者： Cheng, Allen C. Univ Pittsburgh Adv Comp Technol Lab Dept Elect & Comp Engn Pittsburgh PA 15260 USA

ISBN: (纸本)9780769531175

Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability;while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily on adopting special-purpose accelerators (SPA) to take charge of the heavy lifting in the aimed embedded SoC designs. these SPAs, synthesized from either ASIC or FPGA, are usually augmented to the base processor as co-processors to execute the performance-critical regions of applications. ASIC-based SPAs achieve performance-energy efficiency at the expense of sacrificing post-manufacturing programmability while incurring large NRE and TTM;FPGA-based SPAs retain programmability at the expense of significant energy and area increase. Furthermore, augmenting these SPAs as co-processors adds considerable communication and synchronization overhead severely compromising their initially promised benefits. this paper proposes an innovative design paradigm that moves away from the common scheme of adding co-processing ASIC/FPGA SPAs to an integrated and reconfigurable design. Specifically, we propose a new class of embedded processor by replacing the processor's conventional ALU with a more powerful and flexible Versatile Processing Unit (VPU). VPU enables multiple interdependent instructions to be fused and processed together as a single atomic VPU instruction by exploring dataflow dependencies of the application code. the instruction fusion is automatically performed by a VPU-aware compiler. the optimized VPU code reduces code size and amplifies the effective processor bandwidth and capacity by eliminating transient computation and register spill code. Experimental results show up to 400% and average 150% speedup for MediaBench with negligible area increase.

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