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检索条件"任意字段=ACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays"

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HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond 24

HLSFactory: A Framework Empowering High-Level Synthesis Data...

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6th international symposium on Machine Learning for CAD (MLCAD)

作者： Abi-Karam, Stefan Sarkar, Rishov Seigler, Allison Lowe, Sean Wei, Zhigang Chen, Hanqiu Rao, Nanditha John, Lizy Arora, Aman Hao, Cong Georgia Inst Technol Atlanta GA 30332 USA Georgia Tech Res Inst Atlanta GA 30332 USA Univ Texas Austin Austin TX USA Arizona State Univ Tempe AZ USA Int Inst Informat Technol Bangalore Bangalore Karnataka India

ISBN: (数字)9798350363562

ISBN: (纸本)9798400706998

Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the scarcity of accessible highquality HLS datasets and the complexity of building such datasets present great challenges to FPGA and ML researchers. Existing datasets either cover only a subset of previously published benchmarks, provide no way to enumerate optimization design spaces, are limited to a specific vendor, or have no reproducible and extensible software for dataset construction. Many works also lack user-friendly ways to add more designs to existing datasets, limiting wider adoption and sustainability of such datasets. In response to these challenges, we introduce HLSFactory, a comprehensive framework designed to facilitate the curation and generation of high-quality HLS design datasets. HLSFactory has three main stages: 1) a design space expansion stage to elaborate single HLS designs into large design spaces using various optimization directives across multiple vendor tools, 2) a design synthesis stage to execute HLS and FPGA tool flows concurrently across designs, and 3) a data aggregation stage for extracting standardized data into packaged datasets for ML usage. this tripartite architecture not only ensures broad coverage of data points via design space expansion but also supports interoperability with tools from multiple vendors. Users can contribute to each stage easily by submitting their own HLS designs or synthesis results via provided user APIs. the framework is also flexible, allowing extensions at every step via user APIs with custom frontends, synthesis tools, and scripts. To demonstrate the framework functionality, we include an initial set of built-in base designs from PolyBench, MachSuite, Rosetta, CHStone, Kastner et al.'s Parallel Programming for FPGAs, and curated kernels from existing open-source HLS designs. We report the statistical analyses and design space

关键词： Solid modeling Statistical analysis Buildings Machine learning Benchmark testing Software Space exploration Sustainable development field programmable gate arrays Optimization

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the re-configurable delay-insensitive FLYSIG architecture 13th

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13th international Parallel Processing symposium, IPPS 1999 Held in Conjunction with the 10th symposium on Parallel and Distributed Processing, SPDP 1999

作者： Hardt, Wolfram Rettberg, Achim Kleinjohann, Bemd Cooperative Computing and Communication Laboratory Siemens AG and University Paderborn Fürstenallee 11 PaderbornD-33 102 Germany

ISBN: (纸本)3540658319

this article describes a new re-configurable architecture design suitable for high performance signal processing applications. the main benefits beside re-configurability are high computation performance, robustness against technology changes, and short design time. therefore four design paradigms are combined: re-configurable functionality, data-flow orientation, delay-insensitive implementation, and pipelined bit-serial operators. Based on this paradigms a re-configurable high performance processor for cyclic execution of real-time critical algorithms, i.e. a specialized application domain has been designed. Comparable to FPGA based designs operators and interconnections are configurable. In contrast to FPGAs the basic configurable parts are much more complex. this ensures feasibility of complex designs and high complexity the implementation follows a bottom up approach while the concept has been specified top-down. © Springer-Verlag Berlin Heidelberg 1999.

关键词： field programmable gate arrays (FPGA)

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Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only) 10

Towards 5ps resolution TDC on a dynamically reconfigurable F...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Marc-Andre Daigneault Jean Pierre David École Polytechnique de Montréal Montreal PQ Canada

ISBN: (纸本)9781605589114

this paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. the TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. the proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. the results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.

关键词： field programmable gate array time-to-digital converter vernier method dynamic reconfiguration

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Demo abstract: A compact, inexpensive, and battery-powered software-defined radio platform

Demo abstract: A compact, inexpensive, and battery-powered s...

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international symposium on Information Processing in Sensor Networks (IPSN)

作者： Ye-Sheng Kuo thomas Schmid Prabal Dutta EECS Department University of Michigan Ann Arbor MI ECE Department University of Utah Salt Lake City UT

ISBN: (纸本)9781479964703

We present μSDR, a compact, inexpensive, and battery-powered software-defined radio (SDR) platform built on a single-chip, flash-based FPGA fabric and ARM Cortex-M3 processor, enabling lower power and tighter hardware/soft-ware integration than prior commodity SDR platforms. Our architecture, unlike prior designs, is well-suited to hand-held or battery-operated systems and also supports cleaner partitioning since hardware can be easily mapped into the software addresses space, and vice versa. Building on this flexibility, we show how highly time-critical MAC protocols can be implemented on this platform and deployed using just AAA batteries.

关键词： Hardware field programmable gate arrays Protocols throughput Computer architecture Performance evaluation Baseband

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Demo: Ultra-constrained sensor platform interfacing

Demo: Ultra-constrained sensor platform interfacing

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international symposium on Information Processing in Sensor Networks (IPSN)

作者： Pat Pannuto Yoonmyung Lee Ben Kempke Dennis Sylvester David Blaauw Prabal Dutta University of Michigan Ann Arbor MI US Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI

ISBN: (纸本)9781479964703

In this work we expose the challenges of interfacing both conventional and new systems with an extremely resource constrained platform. We find that even when attempts are made to utilize an industry standard protocol (I2C), necessary protocol modifications for ultra-low power design means that interfacing remains non-trivial. We present a functional 0.4mm × 0.8mm ARM Cortex M0 with 3KB of RAM, 24 GPIOs, and an ultra-low power I2C interface. this chip is part of the Michigan Micro Mote (M3) project, which is designed to build a complete software and hardware platform for general purpose sensing at the millimeter scale. We demo an I2C interface circuit allowing commercial hardware to program and interact with the chip and present the beginning of the millimeter scale sensing revolution.

关键词： Low-power electronics Clocks Protocols Hardware field programmable gate arrays Sensors Resistors

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the design of a low energy FPGA 99

The design of a low energy FPGA

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international symposium on Low Power Electronics and Design (ISLPED)

作者： V. George Hui Zhang J. Rabaey Berkeley Wireless Research Center University of California Berkeley CA USA

ISBN: (纸本)9781581131338

this work presents the design of an energy efficient FPGA architecture. Significant reduction in the energy consumption is achieved by tackling both circuit design and architecture optimization issues concurrently. A hybrid interconnect structure incorporating nearest neighbor connections, symmetric mesh architecture, and hierarchical connectivity is used. the energy of the interconnect is also reduced by employing low-swing circuit techniques. these techniques have been employed to design and fabricate an FPGA. Preliminary analysis show energy improvement of more than an order of magnitude when compared to existing commercial architectures.

关键词： field programmable gate arrays Integrated circuit interconnections Computer architecture Power dissipation Energy efficiency Energy consumption Clocks Frequency Logic Switches

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CReconfigurable finite field instruction set architecture 07

CReconfigurable finite field instruction set architecture

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Proceedings of the 2007 acm/sigda 15th international symposium on field programmable gate arrays

作者： Nathan Jachimie Fernando Martinez-Vallin Jafar Saniie Illinois Institute of Technology Chicago Illinois

ISBN: (纸本)9781595936004

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite field Extensions Unit with MicroBlaze processor in a Xilinx Virtex2Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2163 ) multiplier, a speed-up factor of 1530X has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.

关键词： FSL instruction set extensions Xilinx fast simplex links galois fields MicroBlaze embedded development partial reconfiguration finite field arithmetic

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FPGA implementation of highly parallelized decoder logic for network coding (abstract only) 10

FPGA implementation of highly parallelized decoder logic for...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Sunwoo Kim Won W. Ro Yonsei University Seoul South Korea

ISBN: (纸本)9781605589114

Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programmable gate-array (FPGA). A Galois field arithmetic logic unit (GF ALU) is implemented with a full parallelization. We claim that the complexity of hardware is reduced by use of the log and anti-log tables. In addition, the fast arithmetic operation is achieved by the parallelized GF ALU architecture, which allows one-row-calculations of a matrix to be performed concurrently. the decoders for four different sizes of the coefficient matrix have been implemented while the degree of parallelism is preserved for each size. the performance is evaluated by comparing with the performance of the decoding operation both on the ARM processor emulator and a real ARM processor. Using a modern Xilinx Virtex-5 device, the decoding time of 3.5 ms for the size 16 x 16 and 190.5 ms for 128 x 128 has been achieved at the operating frequency of 50MHz, which is equal to 12.7 and 21.7 in terms of speedup.

关键词： network coding fpga fpga implementation galois field arithmetic

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A programmable majority logic array using molecular scale electronics 06

A programmable majority logic array using molecular scale el...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Garrett S. Rose Mircea R. Stan University of Virginia Charlottesville VA

ISBN: (纸本)9781595932921

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. this architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. through this work we show how molecular electronics naturally allows for 3D integration at the *** design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). these switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

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FPGA-based fine-grain parallel computing (abstract only) 11

FPGA-based fine-grain parallel computing (abstract only)

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Andrew W. Hill Andrea Di Blas Richard Hughey University of California Santa Cruz Santa Cruz CA USA

ISBN: (纸本)9781450305549

FPGAs are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging FPGAs to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of FPGAs for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of FPGAs. the design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.

关键词： system on a programmable chip simd parallel computing

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