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检索条件"任意字段=ACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays"

共 225 条记录，以下是31-40 订阅

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A Synthesizable Datapath-Oriented Embedded FPGA Fabric 07

A Synthesizable Datapath-Oriented Embedded FPGA Fabric

引用

15th acm/sigda international symposium on field-programmable gate arrays

作者： Wilton, Steve J. E. Ho, C. H. Leong, Philip H. W. Luk, Wayne Quinton, Brad Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

We present an architecture for a synthesizable datapath-oriented field programmable gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core.

关键词： field programmable gate Array Datapath Synthesis Integrated Circuit System-on-Chip Embedded Block

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the Stratix™ routing and logic architecture

The Stratix™ routing and logic architecture

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lewis, David Betz, Vaughn Jefferson, David Lee, Andy Lane, Chris Leventis, Paul Marquardt, Sandy McClintock, Cameron Pedersen, Bruce Powell, Giles Reddy, Srinivas Wysocki, Chris Cliff, Richard Rose, Jonathan Altera Corporation 101 Innovation Drive San Jose CA 95134 United States Altera Toronto Technology Centre 151 Bloor St W. Toronto Ont. M5S 1S4 Canada

this paper describes the Altera Stratix logic and routing architecture. the primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. the Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, its direct-drive routing which reduces both area and delay. the logic array block and logic cell design is also described, and new routing structures with in the logic array block, and logic element features are described.

关键词： field programmable gate arrays

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A communication architecture for complex runtime systems and its implementation on spartan-3 FPGAs

A communication architecture for complex runtime systems and...

引用

7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Koch, Dirk Beckhoff, Christian Teich, Jürgen University of Erlangen-Nuremberg Am Weichselgarten 3 D91058 Erlangen Germany

ISBN: (纸本)9781605584102

In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by FPGA reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. the paper points out, that the capabilities of Spartan-3 FPGAs are sufficient to build complex reconfigurable systems. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Stochastic, spatial routing for hypergraphs, trees, and meshes

Stochastic, spatial routing for hypergraphs, trees, and mesh...

引用

acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Huang, Randy Wawrzynek, John DeHon, André UC Berkeley Soda Hall 1776 Berkeley CA 94720 United States Dept. of CS 256-80 California Institute Technology Pasadena CA 91125 United States

FPGA place and route is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle preventing late-bound hardware and design mapping for reconfigurable systems. Previous work showed that hardware-assisted routing can accelerate fanout-free routing on Fat-Trees by three orders of magnitude with modest modifications to the network itself. In this paper, we show how these techniques can be applied to any FPGA and how they can be implemented on top of LUT networks in cases where modification of the FPGA itself is not justified. We further show how to accommodate fanout and how to achieve comparable route quality to software-based methods. For a tree network, we estimate an FPGA implementation of our routing logic could route the Toronto Place and Route Benchmarks at least two orders of magnitude faster than a software Pathfinder while achieving within 3% of the aggregate quality. Preliminary results on small mesh benchmarks achieve within one track of vpr -fast.

关键词： field programmable gate arrays

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Placement-driven technology mapping for LUT-based FPGAs

Placement-driven technology mapping for LUT-based FPGAs

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Lin, Joey Y. Jagannathan, Ashok Cong, Jason

In this paper, we study the problem of placement-driven technology mapping for table-lookup based FPGA architectures to optimize circuit performance. Early work on technology mapping for FPGAs such as Chortle-d[14] and Flowmap[3] aim to optimize the depth of the mapped solution without consideration of interconnect delay. Later works such as Flowmap-d[7], Bias-Clus[4] and EdgeMap consider interconnect delays during mapping, but do not take into consideration the effects of their mapping solution on the final placement. Our work focuses on the interaction between the mapping and placement stages. First, the interconnect delay information is estimated from the placement, and used during the labeling process. A placement-based mapping solution which considers both global cell congestion and local cell congestion is then developed. Finally, a legalization step and detailed placement is performed to realize the design. We have implemented our algorithm in a LUT based FPGA technology mapping package named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC benchmarks. We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3% on the average.

关键词： field programmable gate arrays

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Architecture evaluation for power-efficient FPGAs

Architecture evaluation for power-efficient FPGAs

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acm/sigda 11th acm international symposium on field programmable gate arrays

作者： Li, Fei Chen, Deming He, Lei Cong, Jason Electrical Engineering Department University of California Los Angeles CA 90095 United States Computer Science Department University of California Los Angeles CA 90095 United States

this paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs;(ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays;(iii) We develop a cycle-accurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power;(iv) Using the frame work fpgaEVA-LP, we study the power efficiency of FPGAs, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different FPGA components and shed light on the potential opportunities of power optimization for future FPGA designs (e.g., ≤ 0.10um technology).

关键词： field programmable gate arrays

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Architectural Improvements for field programmable Counter arrays: Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs 08

Architectural Improvements for Field Programmable Counter Ar...

引用

16th acm/sigda international symposium on field-programmable gate arrays

作者： Cevrero, Alessandro Athanasopoulos, Panagiotis Parandeh-Afshar, Hadi Verma, Ajay K. Brisk, Philip Gurkaynak, Frank K. Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Inst Microelect & Microsyst Microelect Syst Lab CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

the field programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA;the remaining portion of the circuit is synthesized on the FPGA. this paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an FPGA containing six FPCAs, we observed average and maximum speedups of 1.60x and 2.40x on a set of arithmetic benchmarks.

关键词： FPGA field programmable Counter Array (FPCA)

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Is marriage in the cards for programmable logic, microprocessors and ASICs?

Is marriage in the cards for programmable logic, microproces...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Anon

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Wirelength modeling for homogeneous and heterogeneous FPGA architectural development

Wirelength modeling for homogeneous and heterogeneous FPGA a...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Smith, Alastair M. Das, Joydip Wilton, Steven J.E. Department of Electrical and Computer Engineering University of British Columbia Canada

ISBN: (纸本)9781605584102

this paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. For homogeneous FPGAs, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous FPGAs, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to FPGA architectural design are also presented. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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A Fast Discrete Placement Algorithm for FPGAs 12

A Fast Discrete Placement Algorithm for FPGAs

引用

20th acm/sigda international symposium on field-programmable gate arrays (FPGA)

作者： Wu, Qinghong McElvain, Kenneth S. Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)9781450311557

Good FPGA placement is crucial to obtain the best Quality of Results (QoR) from FPGA hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, FPGAs are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. therefore, discrete FPGA-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. this paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.

关键词： Computer-aided design (CAD) individual cell temperature window masking dynamic window field-programmable gate array (FPGA) placement simulated annealing

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