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检索条件"任意字段=ACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays"
225 条 记 录,以下是51-60 订阅
排序:
New retiming-based technology mapping algorithm for LUT-based FPGAs
New retiming-based technology mapping algorithm for LUT-base...
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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA
作者: Pan, Peichen Lin, Chih-Chang Clarkson Univ Potsdam United States
In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based field programmable gate arrays. the algorithm is based on a novel iterative procedure for computing all k-cuts of all... 详细信息
来源: 评论
Eliminating the Memory Bottleneck: An FPGA-based Solution for 3D Reverse Time Migration  11
Eliminating the Memory Bottleneck: An FPGA-based Solution fo...
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19th Annual acm international symposium on field-programmable gate arrays
作者: Fu, Haohuan Clapp, Robert G. Tsinghua Univ Ctr Earth Syst Sci Beijing 100084 Peoples R China
Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale with t... 详细信息
来源: 评论
Embedded floating-point units in FPGAs  06
Embedded floating-point units in FPGAs
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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006
作者: Beauchamp, Michael J. Hauck, Scott Underwood, Keith D. Hemmert, K. Scott University of Washington Dept. of Electrical Engineering United States Sandia National Laboratories Scalable Computing Systems United States
Due to their generic and highly programmable nature, FPGAs provide the ability to implement a wide range of applications. However, it is this nonspecific nature that has limited the use of FPGAs in scientific applicat... 详细信息
来源: 评论
Wire type assignment for FPGA routing
Wire type assignment for FPGA routing
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acm/sigda 11th acm international symposium on field programmable gate arrays
作者: Lee, Seokjin Xiang, Hua Wong, D.F. Sun, Richard Y. Dept. of Elec. and Comp. Eng. The Univ. of Texas at Austin Austin TX 78712 United States Department of Elec. and Comp. Eng. Univ. Illinois at Urbana-Champaign Urbana IL 61801 United States Xilinx Inc. 2100 Logic Drive San Jose CA 95124 United States
the routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently developed FPGAs (e.g., Virtex-II), there a... 详细信息
来源: 评论
Architecture-Specific Packing for Virtex-5 FPGAs  08
Architecture-Specific Packing for Virtex-5 FPGAs
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16th acm/sigda international symposium on field-programmable gate arrays
作者: Ahmed, Taneem Kundarewich, Paul D. Anderson, Jason H. Taylor, Brad L. Aggarwal, Rajat Xilinx Inc Toronto ON Canada
We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA - the Xilinx (R) Virtex (TM) -5 FPGA. Two aspects of packin... 详细信息
来源: 评论
Energy-efficient signal processing using FPGAs
Energy-efficient signal processing using FPGAs
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acm/sigda 11th acm international symposium on field programmable gate arrays
作者: Choi, Seonil Scrofano, Ronald Prasanna, Viktor K. Jang, Ju-Wook Dept. of Elec. Engineering Systems University of Southern California Los Angeles CA United States Department of Electronic Engineering Sogang University Seoul Korea Republic of
In this paper, we present techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast ... 详细信息
来源: 评论
Clock power reduction for virtex-5 FPGAs
Clock power reduction for virtex-5 FPGAs
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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09
作者: Wang, Qiang Gupta, Subodh Anderson, Jason Xilinx Inc. Logic Drive San Jose CA 95124 United States ECE Dept Univ. of Toronto King's College Road Toronto ON M5S 3G4 Canada
Clock network power in field-programmable gate arrays (FP- ) is considered and two complementary approaches for power reduction in the Xilinx RVirtexTM-5 FPGA are. the approaches are unique in that they lever- specifi... 详细信息
来源: 评论
An iterative division algorithm for FPGAs  06
An iterative division algorithm for FPGAs
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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006
作者: Liu, Jianhua Chang, Michael Cheng, Chung-Kuan Computer Science and Engineering Department University of California San Diego 92093 United States
Division is one of the most complicated and expensive arithmetic operations. Both clock frequency and operation delay are limited by the memory wall, even in LUT-based FPGA devices. To conquer the memory limitation, w... 详细信息
来源: 评论
A novel FPGA logic block for improved arithmetic performance  08
A novel FPGA logic block for improved arithmetic performance
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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008
作者: Parandeh-Afshar, Hadi Brisk, Philip Ienne, Paolo School of Computer and Communication Sciences CH-1015 Lausanne Switzerland
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. the new cell features additional fast carry-chains that concatenate adja... 详细信息
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Improvements to technology mapping for LUT-based FPGAs  06
Improvements to technology mapping for LUT-based FPGAs
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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006
作者: Mishchenko, Alan Chatterjee, Satrajit Brayton, Robert Department of EECS University of California Berkeley United States
the paper presents several improvements to state-of-the-art in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD '04]. Improved cut enumeration computes all K-... 详细信息
来源: 评论