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检索条件"任意字段=ACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays"

共 225 条记录，以下是71-80 订阅

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Flexible multi-mode embedded floating-point unit for field programmable gate arrays

Flexible multi-mode embedded floating-point unit for field p...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Chong, Yee Jern Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781605584102

Performance of field programmable gate arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floatingpoint units on FPGAs consume a large amount of resources. this makes FPGAs less attractive for use in floating-point intensive applications. therefore, there is a need for embedded floating-point units (FPUs) in FPGAs. However, if unutilized, embedded FPUs waste space on the FPGA die. To overcome this issue, we propose a flexible multi-mode embedded FPU for FPGAs that can be configured to perform a wide range of operations. the floating-point adder and multiplier in our embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on our FPGA with embedded FPU blocks. the results using our embedded FPUs showed a mean area improvement of 5.2 times and a mean delay improvement of 5.8 times for the doubleprecision benchmarks, and a mean area improvement of 4.4 times and a mean delay improvement of 4.2 times for the single-precision benchmarks. Copyright 2009 acm.

关键词： Adders

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A 90nm low-power FPGA for battery-powered applications 06

A 90nm low-power FPGA for battery-powered applications

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14th acm/sigda international symposium on field programmable gate arrays - FPGA 2006

作者： Tuan, Tim Kao, Sean Rahman, Arif Das, Satyaki Trimberger, Steve Xilinx Research Labs 2100 Logic Dr. San Jose CA 95124 United States

ISBN: (纸本)1595932925

programmable logic devices such as FPGAs are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than ASICs and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications such as those in consumer and automotive markets. Our design uses the Xilinx Spartan-3 low-cost FPGA as a baseline and achieves substantial power savings through a series of power optimizations. the resulting architecture is compatible with existing commercial design tools. the implementation is done in a 90nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode, and wakes up from standby mode in approximately 100ns. Copyright 2006 acm.

关键词： field programmable gate arrays

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Simultaneous logic decomposition with technology mapping in FPGA designs 01

Simultaneous logic decomposition with technology mapping in ...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Chen, G. Cong, J. Computer Science Department University of California Los Angeles CA 90095 United States

ISBN: (纸本)9781581133417

Conventional technology mapping algorithms for SRAM-based field programmable gate arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. the impact of logic decomposition on delay and area of the technology mapping solutions is not well understood. In this paper, we present an algorithm named SLDMap that performs delay-minimized technology mapping on a large set of decompositions and simultaneously controls the mapping area under delay constraints. Our study leads to two conclusions: (1) For depth minimization, the best algorithms in conventional flow (dmig + CutMap) produce satisfactory results with a short runtime, even with a fixed decomposition;(2) When all the structural decompositions of the 6-bounded Boolean network are explored, SLDMap consistently outperforms the state-of-the-art separate flow (dmig + CutMap) by 12% in depth and 10% in area on average;it also consistently outperforms the state-of-the-art combined approach dogma by 8% in depth and 6% in area on average.

关键词： field programmable gate arrays

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Fast and scalable packet classification using perfect hash

Fast and scalable packet classification using perfect hash

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Puš, Viktor Korenek, Jan CESNET z. s. p. o. Zikova 4 160 00 Prague Czech Republic Faculty of Information Technology Brno University of Technology Bozetechova 2 612 66 Brno Czech Republic

ISBN: (纸本)9781605584102

Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them cancompete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. the solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. the algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. this makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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A memory coherence technique for online transient error recovery of FPGA configurations 01

A memory coherence technique for online transient error reco...

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2001 acm/sigda 9th international Sysmposium on field programmable gate arrays (FPGA 2001)

作者： Huang, W.-J. McCluskey, E.J. Center for Reliable Computing Department of Electrical Engineering Stanford University Stanford CA 94305-4055 United States

ISBN: (纸本)9781581133417

the partial reconfiguration feature of some of the current-generation field programmable gate arrays (FPGAs) can improve dependability by detecting and correcting errors in on-chip configuration data. Such an error recovery process can be executed online with minimal interference of user applications. However, because Look-up Tables (LUTs) in Configurable Logic Blocks (CLBs) of FPGAs can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. In this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory-configured LUTs. theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications.

关键词： field programmable gate arrays

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Towards reliable 5Gbps wave-pipelined and gbps surfing interconnect in 65nm FPGAs

Towards reliable 5Gbps wave-pipelined and gbps surfing inter...

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7th acm sigda international symposium on field-programmable gate arrays, FPGA'09

作者： Teehan, Paul Lemieux, G.F. Greenstreet, R. Dept. of ECE University of British Columbia Canada Dept. of Computer Science University of British Columbia Canada

ISBN: (纸本)9781605584102

FPGA user clocks are slow enough that only a fraction of the interconnect's is actually used. there may be an opportunity use throughput-oriented interconnect to decrease routing and wire area using on-chip serial signaling, especially datapath designs which operate on words instead of bits. To so, these links must operate reliably at very high bit rates. We wave pipelining and surfing source-synchronous schemes the presence of power supply and crosstalk noise. In particular, noise is a critical modeling challenge;better models are for FPGA power grids. Our results show that wave pipelining operate at rates as high as 5Gbps for short links, but it is sensitive to noise in longer links and must run much slower to reliable. In contrast, surfing achieves a stable operating bit rate of 3Gbps and is relatively insensitive to noise. Copyright 2009 acm.

关键词： field programmable gate arrays (FPGA)

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Coarse-grained FPGA architecture for high-performance FIR filtering

Coarse-grained FPGA architecture for high-performance FIR fi...

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Proceedings of the 1998 acm/sigda 6th international symposium on field programmable gate arrays, FPGA

作者： Anderson, James R. Sheth, Siddharth Roy, Kaushik Intel Corp Santa Clara United States

this paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. the proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.

关键词： field programmable gate arrays

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TORCH: A design tool for routing channel segmentation in FPGAs 08

TORCH: A design tool for routing channel segmentation in FPG...

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16th acm/sigda international symposium on field-programmable gate arrays, FPGA 2008

作者： Lin, Mingjie Gamal, Abbas El Department of Electrical Engineering Stanford University CA 94305 United States

ISBN: (纸本)9781595939340

A design tool for routing channel segmentation in island-style FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing channel segmentation using the average interconnect power-delay product as a performance metric, which is estimated from placed and routed designs. A simulated- annealing procedure is used, whereby segmentation is incrementally changed in each iteration, the benchmark designs are mapped using VPR, and the performance metric is computed to decide whether to accept or reject the new segmentation. Run time is signi cantly reduced by using incremental routing in each iteration and parallelizing the metric evaluation. Experimental results using the MCNC benchmark designs demonstrate an average of 22% and 15% reduction in delay and power relative to a baseline segmentation. the results also show that average segment length should decrease with technology scaling. Finally, we demonstrate how the tool can be used to optimize other aspects of programmable routing in an FPGA. Copyright 2008 acm.

关键词： field programmable gate arrays (FPGA)

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Prototyping globally Asynchronous locally synchronous circuits on commercial synchronous FPGAs

Prototyping globally Asynchronous locally synchronous circui...

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acm/sigda thirteenth acm international symposium on field programmable gate arrays - FPGA 2005

作者： Najibi, Mehrdad Saleh, Kamran Naderi, Mohsen Pedram, Hossein Sedighi, Mehdi 424 Hafez Ave. Tehran 15785 Iran

this paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. the library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. the results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.

关键词： field programmable gate arrays

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Towards Scalable FPGA CAD through Architecture 11

Towards Scalable FPGA CAD Through Architecture

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19th Annual acm international symposium on field-programmable gate arrays

作者： Chin, Scott Y. L. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450305549

Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities. Already, compile times on the order of a day are common, and the situation will only get worse as FPGAs get larger. Without a concerted effort to reduce compile times, further scaling of FPGAs will eventually become impractical. Previous works have presented fast CAD tools that tradeoff quality of result for compile time. In this paper, we take a different but complementary approach. We show that the architecture of the FPGA itself can be designed to be amenable to fast-compile. If not done carefully, this can lead to lower-quality mapping results, so a careful tradeoff between area, delay, power, and compile run-time is essential. We investigate the extent to which run-time can be reduced by employing high-capacity logic blocks. We extend previous studies on logic block architectures by quantifying the area, delay and CAD runtime trade-offs for large capacity blocks, and also investigate some multi-level logic block architectures. In addition, we present an analytically derived equation to guide the design of logic block I/O requirements.

关键词： field-programmable gate arrays FPGAs Architecture CAD Run-time

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