fieldprogrammablegatearrays (fpgas) play many important roles, ranging from small glue logic replacement to System-on-Chip (SoC) designs. Nevertheless, fpga vendors cannot accurately specify the power consumption o...
详细信息
fieldprogrammablegatearrays (fpgas) play many important roles, ranging from small glue logic replacement to System-on-Chip (SoC) designs. Nevertheless, fpga vendors cannot accurately specify the power consumption of their products on device data sheets because the power consumption of fpgas is strongly dependent on the target circuit, including resource utilization, logic partitioning, mapping, placement and routing. Although major CAD tools have started to report average power consumption under given transition activities, power-efficient fpga design demands more detailed information about power consumption. In this paper, we introduce an in-house cycle-accurate fpga energy measurement tool and energy characterization schemes spanning low-level to high-level design. This tool offers all the capabilities necessary to investigate the energy consumption of fpgas for operation-based energy characterization, which is applicable to high-level and system-wide energy estimation. It also includes features for low-level energy characterization. We compare our tool with Xilinx XPower and demonstrate the state-machine-based energy characterization of an SDRAM controller.
Multi-point distributed random variables whose moments match those of a Gaussian random variable up to a certain order play an important role in Monte Carlo simulations of weak approximations of stochastic differentia...
ISBN:
(纸本)9781595930293
Multi-point distributed random variables whose moments match those of a Gaussian random variable up to a certain order play an important role in Monte Carlo simulations of weak approximations of stochastic differential equations. In applications such as finance, where "real time" execution is required, there is a strong need for highly efficient implementations. In this paper a fast and flexible dedicated hardware solution on a fieldprogrammablegate Array (fpga) is presented. A comparative performance analysis between a software-only and the proposed hardware solution demonstrates that the fpga solution is bottleneck-free, retains the flexibility of the software solution and significantly increases the computational efficiency.
This article is a concise literature review of the actual state of the art in arithmetic for field-programmablegatearrays (fpgas), including studies, implementation techniques, operators, and structures, in various ...
ISBN:
(纸本)9781595930293
This article is a concise literature review of the actual state of the art in arithmetic for field-programmablegatearrays (fpgas), including studies, implementation techniques, operators, and structures, in various area-time tradeoffs. It covers the integer operations of addition/subtraction, multiplication, squaring, division, and square root, in parallel, and in both serial modes (least-significant digit first, and online). Many people, including researchers in the field of computer arithmetic, parallel computing, digital signal and image processing, system-on-a-programmable chip (SoPC) designers, and other people with a need to implement special purpose arithmetic circuits on fpgas, might find such a review useful, either as an introduction to the topic, as a knowledge update, or for reference.
This paper presents a new universal test approach for fpga logic resources. It includes a new greedy configuration-generating algorithm, and a new fpga Configurable Logic Block (CLB) test model. The model is based on ...
ISBN:
(纸本)9781595930293
This paper presents a new universal test approach for fpga logic resources. It includes a new greedy configuration-generating algorithm, and a new fpga Configurable Logic Block (CLB) test model. The model is based on two directed graphs: a structure graph and a configuration graph, which convey the important information from the CLB gate level circuit to the greedy configuration-generating algorithm, so the algorithm can generate minimum the number of test configurations to achieve a given fault coverage. With this new approach, researchers can easily get test patterns optimized both in test time and fault coverage for different fpga architectures. At the end, we compare experiment results with other test approaches, and the results show test pattern from the new approach is even more efficient than pattern from manual optimization. It also proves that the approach can deal with different types of fpgas very well.
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