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检索条件"任意字段=ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005"

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Dynamic reconfiguration in fpga-based SoC designs (abstract only) 05

Dynamic reconfiguration in FPGA-based SoC designs (abstract ...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Roman Bartosinski Martin Daněk Petr Honzík Rudolf Matoušek Czech Academy of Sciences Czech Republic

ISBN: (纸本)9781595930293

This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets. Further a sample application is discussed that uses a dynamically reconfigurable fpga to implement different floating-point calculations in hardware, reconfigured as required by the execution of the user code. The implementation data for two dynamically reconfigurable platforms available on the market - the Xilinx Virtex2 family fpgas and the Atmel FPSLIC family fpgas - is compared in terms of resource requirements, operating frequency, and power consumption.

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Dual-Vt fpga design for leakage power reduction (abstract only) 05

Dual-Vt FPGA design for leakage power reduction (abstract on...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Akhilesh Kumar Mohab Anis University of Waterloo Waterloo Ontario

ISBN: (纸本)9781595930293

Leakage power has been overshadowed by dynamic power minimization techniques in fpgas, and is a growing concern in programmable logic. This paper proposes a dual threshold voltage implementation of the fpga architecture for leakage power reduction. A CAD flow is developed for assigning high threshold voltage to the logic elements within the logic blocks of the fpga for leakage power reduction. The CAD flow ensures that all the logic blocks remain identical with respect to the number of high and low threshold voltage logic elements that each logic block contains. This CAD flow leads to a dual threshold voltage implementation for the fpga architecture. Results indicate that over 95% of the logic elements in the fpga can be assigned high threshold voltage. On an average leakage savings of 60% and up to 70% for some benchmarks can be achieved. The proposed CAD flow forms a basis on which other dual threshold voltage implementations of fpga can be evaluated. We investigate the design trade-offs between the ratio of the number of high and number of low-Vt logic elements in a cluster and the leakage savings. We also investigate the impact of cluster size on leakage savings for the dual threshold voltage implementation.

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Choice of base revisited: higher radices for fpga-based floating-point computation (abstract only) 05

Choice of base revisited: higher radices for FPGA-based floa...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Bryan C. Catanzaro Brent E. Nelson Brigham Young University Provo Utah

ISBN: (纸本)9781595930293

The general computing world settled on radix 2 floating point representations over three decades ago. The analyses which led to this choice were all based on the underlying premise that the goal of a floating-point representation is to maximize numerical accuracy per bit of data. However, the unique nature of fpga-based computations makes numerical accuracy per unit of fpga resources a more important measure by which to judge the usefulness of a given floating point representation. Due to the high cost of shifters as implemented on fpgas, higher radix floating-point representations are uniquely suited to fpga-based computations, especially high precision calculations which require the support of denormalized numbers. Higher radix representations use fpga resources more efficiently. For example, a radix 16 adder requires 20% less LUTs than its radix 2 counterpart, while delivering equal worst-case and better average case numerical accuracy.

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A leakage-aware CAD flow for MTCMOS fpga architectures (abstract only) 05

A leakage-aware CAD flow for MTCMOS FPGA architectures (abst...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： H. Hassan M. Anis M. Elmasry University of Waterloo Waterloo Ontario

ISBN: (纸本)9781595930293

fpgas are witnessing a big increase in their applications, especially with the introduction of state-of-the-art fpgas using nanometer technologies. This has been accompanied with a big increase in power dissipation in fpgas, which forms a road block to the integration of fpgas in several hand-held applications. Motivated by the increase in the percentage of leakage power dissipation to the total power dissipation in modern technologies, this work presents a complete CAD flow to mitigate leakage power dissipation in fpgas. The algorithm is based on a fpga architecture that employs multi-threshold CMOS technology. The flow is based on the VPR flow and it aims to pack and place logic blocks that exhibit similar idleness close to each other so that they can be turned off during their idle time. The flow is tested with a CMOS 0.13 m dual-vth technology and achieved an average power saving of 22%.

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A partial reconfigurable fpga implementation for industrial controllers using SFC-petri net description (abstract only) 05

A partial reconfigurable FPGA implementation for industrial ...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Paulo Sérgio B. Nascimento Paulo Romero M. Maciel Manoel E. Lima Remy E. Sant'ana Abel Guilhermino S. Filho Federal University of Pernambuco Recife-PE Brazil

ISBN: (纸本)9781595930293

Sequential Control System in the industry has been used in applications based on programmable Logical Controllers (PLC). These Systems are, in general, highly complex and with an operation cycle around 1ms or 10ms. PLC are, in general, expensive for theses high complex applications. In this work, a Dynamical Reconfigurable approach is presented, based on Xilinx Virtex-II fpga architecture, operating as a virtual hardware machine. In this context, the control process is specified in the industrial standard language SFC/Petri net (Sequential Function Chart). For large controllers, a partial and dynamical reconfiguration mechanism takes place and the controller is split into multiple contexts, which are sequentially executed within the same fpga, without violating the operation cycle of the system, in spite of the reconfiguration overhead. The solution is cost compatible with current PLC for complex applications and can reach better performance by exploration of the potential parallelism of control descriptions.

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An fpga based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only) 05

An FPGA based SDRAM controller with complex QoS scheduling a...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Sven Heithecker Rolf Ernst Technical University of Braunschweig Braunschweig Germany

ISBN: (纸本)9781595930293

Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multi-stream access with different QoS (Quality of Service) requirements is involved. At SIPS 2003 conference, we presented a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard real-time constraints for periodic video signals and hard real-time bursty accesses for video coprocessors. To handle these contradictory QoS requirements at high system performance, a combination of an 2-stage scheduling algorithm and static priorities was used. This poster describes an additional flow control which greatly enhances the overall performance and controlability. The efficient but simple controller design makes the controller well suited for fpga based designs. Experiments with our fpga based high-end video platform demonstrate the superiority of this architecture.

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Firm-core Virtual fpga for Just-in-Time fpga Compilation (abstract only) 05

Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (ab...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Roman Lysecky Kris Miller Frank Vahid Kees Vissers University of California Riverside Riverside CA

ISBN: (纸本)9781595930293

Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures, yielding software portability benefits. We previously introduced the concept of a standard hardware binary to achieve similar portability benefits for hardware, using a JIT compiler to compile the hardware binary to an fpga. Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms that implement the standard hardware binary on a simple custom fpga fabric designed specifically for JIT compilation. While directly implementing a custom fpga fabric on silicon may be feasible for some applications, we investigated the option of implementing the simple fpga fabric as a circuit mapped to a physical fpga - a virtual fpga. We described our simple fabric in structural VHDL, synthesized the fabric onto a Xilinx Spartan-IIE fpga, and mapped 18 benchmark circuits onto the resulting virtual fpga. Our results show a 6X decrease in performance and a 100X increase in hardware resource usage for the virtual fpga approach compared to mapping the circuits directly to the physical fpga. For applications in which hardware portability is essential, a designer could leverage the large capacity of current commercially available fpgas to implement a virtual fpga with tens of thousands of configurable gates, providing about the same amount of configurable logic as fpgas produced in the mid 1990s. Nevertheless, the large overheads clearly indicate the need to develop a virtual fpga approach tuned to physical fabrics in order to reduce the overhead.

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Accelerating mutual information-based 3D medical image registration with An fpga computing platform (abstract only) 05

Accelerating mutual information-based 3D medical image regis...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Jianchun Li Christos Papachristou Raj Shekhar Case Western Reserve University Cleveland OH University of Maryland Baltimore MD

ISBN: (纸本)9781595930293

Mutual information-based 3D image Registration algorithm is shown to be an accurate, robust and more general registration method for medical image processing. However, its potential application in clinic is jeopardized by its high computational costs. Like many other 3D imaging algorithms, 3D registration needs to process vast amount of image data. The intrinsic computing characteristics of the mutual information-based registration algorithm make it even more difficult to manage and cache the input data. In this paper, we introduce our fpga-based computing platform and detail its application in accelerating the mutual information-based 3D image registration. This platform is designed to accelerate a series of 3D medical imaging algorithms dominated by local operations. It is a System-on-Chip (SoC) architecture with an intelligent data caching system for efficient data fetching and buffering. A reconfigurable multi-pipeline execution unit in the platform is designed to perform high-speed parallel computation. This unit can be customized according to different algorithm requirements to achieve high performance. The simulation results for accelerating the mutual information based registration with our platform show that a speed-up of about 30 can be achieved when compared to a single-CPU computer. Moreover, the platform can be easily reconfigured to accelerate other 3D medical imaging algorithms.

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Energy-efficient fpga interconnect architecture design (abstract only) 05

Energy-efficient FPGA interconnect architecture design (abst...

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Rohini Krishnan R. I.M.P. Meijer Durand Guillaume Philips Research Laboratories Eindhoven The Netherlands

ISBN: (纸本)9781595930293

In this work, the design of an energy-efficient fpga interconnect architecture has been investigated. It concerns a dual-supply solution, where the logic blocks are powered by a nominal voltage supply and the interconnect part is powered by a reduced voltage supply. The behaviour of a fully-buffered, a fully pass-transistor based and a hybrid buffer and pass-transistor architecture has been investigated over a range of power supply voltages. It is found that there exists an optimal ratio between the number of pass-transistor and tri-state buffer switches depending on the load and power supply involved. By reducing the signal voltage swing on the interconnect, the need for a fully tri-state buffer-based interconnect is eliminated, thus saving valuable area and *** benchmark studies, it is confirmed that using an optimal composite of pass-transistor and tri-state buffer switches operating at a reduced power supply can meet the same speed as compared to the full-swing scenario at a much lower power consumption. An average reduction in power-delay of 4.4x for low-load critical paths and 2.7x for high-load critical paths is achieved using buffer receivers. Using levelshifter receivers, an average reduction in power-delay of 4.7x for low-load critical paths and 2.8x for high-load critical paths is obtained. It is also found that due to partially replacing tri-state buffers by pass-transistor switches and inspite of using levelshifters, we can save up to a factor of 4x in interconnect area as compared to fully-buffered architectures. The results have been validated over various benchmarks in a 0.13 m CMOS technology.

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The Stratix II logic and routing architecture 05

The Stratix II logic and routing architecture

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： David Lewis Elias Ahmed Gregg Baeckler Vaughn Betz Mark Bourgeault David Cashman David Galloway Mike Hutton Chris Lane Andy Lee Paul Leventis Sandy Marquardt Cameron McClintock Ketan Padalia Bruce Pedersen Giles Powell Boris Ratchev Srinivas Reddy Jay Schleicher Kevin Stevens Richard Yuan Richard Cliff Jonathan Rose Altera Corporation Toronto Ontario Canada Altera Corporation San Jose CA University of Toronto Toronto Ontario Canada

ISBN: (纸本)9781595930293

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.

关键词： logic module routing fpga

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