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My Fifteen Year Journey of Deploying fpga Accelerated Solutions 24

My Fifteen Year Journey of Deploying FPGA Accelerated Soluti...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Prabhat K. Gupta Innovex LLC Portland OR USA

ISBN: (纸本)9798400704185

While fpgas have been investigated for accelerating computing workloads in academia for many decades, industry started adopting fpgas as an accelerator only in the last decade, but even those deployments have been fairly limited. This talk describes my journey over 15 years of building and deploying fpga accelerated solutions. In my career, I have led the integration of fpgas with CPUs in a variety of ways, each seeking the right mix of efficiency, capability, and cost. The first phase of the journey begins at Intel in 2008 in building the first solutions with socketed fpgas attached to Xeon CPUs using FSB and QPI coherent buses. These coherently attached fpgas enabled various new use cases beyond the PCIe attached fpga accelerators leading to projections of wide scale deployment of fpgas in the data center. Intel's acquisition of Altera in 2015 kicked off the second phase where we integrated a fpga die with a Xeon die to produce a multi-chip package that dropped into a Xeon socket. This was introduced in the market targeting communication workloads. We formed Megh Computing in 2017 to enable a fpga accelerated edge platform for analytics workloads in the enterprise which resulted in solutions for video surveillance. The talk will discuss the various challenges and breakthroughs in deploying fpga accelerators from the edge to the datacenter, where I see the market headed in the near future and identify promising directions and tough problems the fpga research community need to tackle to realize the potential of reconfigurable computing.

关键词： accelerators artificial intelligence computer vision cpu + fpga fpga machine learning

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Cross-fpga Power Estimation from High Level Synthesis via Transfer-Learning 24

Cross-FPGA Power Estimation from High Level Synthesis via Tr...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Zhigang Wei Aman Arora Emily Shriver Lizy John The University of Austin at Texas Austin TX USA Arizona State University Tempe AZ USA Intel Labs Hillsboro OR USA

ISBN: (纸本)9798400704185

Machine learning (ML) has been successfully employed to estimate power consumption for fpgas using features derived from post High Level Synthesis (HLS). As a result, the power evaluation of the design bypasses time-consuming logic synthesis and implementation. However, such models have noticeable drawbacks. Firstly, the dataset preparation is time-consuming since researchers invest significant effort in constructing a sufficient dataset to train an accurate model for a target fpga. Secondly, the model trained on one fpga cannot be directly applied to another. Without prior knowledge about the architecture of the second fpga, the model's power estimation on this new fpga is of unknown confidence. To address these challenges, we propose a novel cross-fpga power modeling methodology called XPNet that combines Transfer-Learning with an innovative data selection technique that enables efficient fine-tuning. We start by applying Transfer-Learning with our data selection methodology to adapt a GNN-based power model to a second fpga using only 20 data samples, resulting in 6.53% error. We then explore if our approach works for lighter-weight ML-based models, such as multi-layer perception (MLP), and show less than a 1% degradation in accuracy. Additionally, we explore the impact of using Meta-Learning algorithm on our model and show that with only 40 data samples from the target fpga, the model still manages an error of 6%.

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fpga 2021 Chairs' Welcome

FPGA 2021 - 2021 ACM/SIGDA International Symposium on Field-...

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fpga 2021 - 2021 acm/sigda international symposium on field-programmable gate arrays 2021年 III页

作者： Shannon, Lesley Adler, Michael Simon Fraser University Canada Intel United States

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A scalable and robust hierarchical floorplanning to enable 24-hour prototyping for 100k-LUT fpgas 21

A scalable and robust hierarchical floorplanning to enable 2...

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2021 acm international symposium on Physical Design, ISPD 2021

作者： Gore, Ganesh Tang, Xifan Gaillardon, Pierre-Emmanuel University of Utah Salt Lake CityUT United States

ISBN: (纸本)9781450383004

Physical design for field programmable gate Array (fpga) is challenging and time-consuming, primarily due to the use of a full-custom approach for aggressively optimize Performance, Power and Area (P.P.A.) of the fpga design. The growing number of fpga applications demands novel architectures and shorter development cycles. The use of an automated toolchain is essential to reduce end-to-end development time. This paper presents scalable and adaptive hierarchical floorplanning strategies to significantly reduce the physical design runtime and enable millions-of-LUT fpga layout implementations using standard ASIC toolchains. This approach mainly exploits the regularity of the design and performs necessary feedthrough creations for global and clock nets to eliminate any requirement of global optimizations. To validate this approach, we implemented full-chip layouts for modern fpga fabric with logic capacity ranging from 40 to 100k LUTs using a commercial 12nm technology. Our results show that the physical implementation of a 128k-LUT fpga fabric can be achieved within 24-hours, which has not been demonstrated by any previous work. Compared to previous work, the runtime reduction of 8x is obtained for implementing 2.5k LUTs fpga device. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on fpgas 24

A Flexible, Fast, Low Bandwidth Block-based Acceleration Arc...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Yan Chen Kiyofumi Tanaka Japan Advanced Institute of Science and Technology Nomi Ishikawa Japan

ISBN: (纸本)9798400704185

In recent years, Convolutional Neural Networks (CNNs) have been widely used in many fields. Many accelerators are designed to run CNN inference on hardware. They are classified into two types: Overlay and Dataflow. In this paper, we propose a new architecture of CNN Inference accelerators to leverage the strengths of each type. It is flexible, fast, and has low off-chip memory bandwidth requirements. The accelerator based on our new architecture can be configured to fit the CNN structure and fpga capacity. It basically runs CNNs by blocks, whereas it has a fallback path to run single Convolution or Fully Connected layers efficiently. Our architecture demonstrates significant advantages when running networks composed of inverted residual blocks. We archived 1954FPS (frames per second) when running 8-bit quantized MobileNetV2 on a mid-range fpga ZU7EV, and the off-chip memory bandwidth requirement is as low as 2.47GiB/s. It also runs on cost-optimized fpgas, and archived 505FPS on ZU3EG. The throughputs of ours are higher than the other types, while the minimum fpga capacity and the off-chip memory bandwidth requirement of ours are reasonable.

关键词： convolutional neural network fpga hardware accelerator inverted residual block

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Energy-Efficient 360-Degree Video Rendering on fpga via Algorithm-Architecture Co-Design 20

Energy-Efficient 360-Degree Video Rendering on FPGA via Algo...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Sun, Qiuyue Taherin, Amir Siatitse, Yawo Zhu, Yuhao Univ Rochester Rochester NY 14627 USA

ISBN: (纸本)9781450370998

360 degrees panoramic video provides an immersive Virtual Reality experience. However, rendering 360 degrees videos consumes excessive energy on client devices. fpga is an ideal offloading target to improve the energy-efficiency. However, a naive implementation of the processing algorithm would lead to an excessive memory footprint that offsets the energy benefit. In this paper, we propose an algorithm-architecture co-designed system that dramatically reduces the onchip memory requirement of VR video processing to enable fpga offloading. Evaluation shows that our system is able to achieve significant energy reduction with no loss of performance compared to today's off-the-shelf VR video rendering system.

关键词： Virtual Reality Panoramic Video Perspective Projection Locality

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ISO-TENANT: Rethinking fpga Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in fpga. 24

ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN)...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Muhammed Kawser Ahmed Christophe Bobda University of Florida Gainesville USA

ISBN: (纸本)9798400704185

Although fpgas in cloud applications facilitate customized hardware acceleration, they also introduce new security challenges that demand attention. Granting cloud users, the capability to reconfigure hardware designs after deployment may create potential vulnerabilities for malicious users, thereby jeopardizing entire cloud platforms. Multi-tenant fpga services, where a single fpga is divided spatially among multiple users, are highly vulnerable to such attacks such as remote power side channel attacks, Denial of Service (DoS) attacks and Fault Injection attacks. We propose a novel power distribution network for cloud fpga security using physical CMOS-based galvanic isolation. In this architecture, each tenant is isolated spatially, providing protection against voltage spikes, ground loops, and electrical noise, the key premises of remote power side-channel attacks. The isolation technique is carried out by using reconfigurable MoM (Metal-over-Metal) capacitors and switch banks, along with Power Management and Configuration Controller Unit. By implementing a Custom Configuration Memory (CCM), we aim to provide a dynamic and customizable solution that allows fpga designers to selectively interconnect or isolate groups of Configurable Logic Blocks (CLBs). This approach involves the formation of distinct regions within the fpga, each capable of sourcing power either from a dedicated CMOS isolation power supply or the standard fpga voltage power supply. Our approach, leveraging physical isolation, can successfully prevent such attacks and can be established as the first line of defense for cloud fpga security.

关键词： fpga multi-tenant cloud fpga pdn remote attacks

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Towards Accelerator Customization in Real-time Safety-critical Systems 25

Towards Accelerator Customization in Real-time Safety-critic...

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Proceedings of the 2025 acm/sigda international symposium on field programmable gate arrays

作者： Shixin Ji Xingzhen Chen Wei Zhang Zhuoping Yang Jinming Zhuang Sarah Schultz Yukai Song Jingtong Hu Alex K. Jones Zheng Dong Peipei Zhou Brown University Providence USA University of Pittsburgh Pittsburgh USA Syracuse University Syracuse USA Wayne State University Detroit USA

ISBN: (纸本)9798400713965

Real-time requirements are essential for safety-critical systems such as autonomous driving and robotics. In these systems, schedulability - ensuring every task completes before its deadline - is critical, as missing even a single deadline can lead to catastrophic consequences. Unlike Quality-of-Service (QoS) or service-level agreement (SLA) metrics, where occasional deadline misses are tolerable, time-predictable safety-critical systems demand strict adherence to deadlines. Existing multi-task scheduling frameworks, optimized for QoS/SLA, fail to meet these requirements, even when incorporating real-time techniques like preemption and *** fpga-based systems, accelerators are widely used to handle real-time computational tasks. While existing accelerators focus on low latency and high throughput, these optimizations are insufficient when multiple tasks share a single accelerator, as low latency alone does not ensure schedulability. For example in Fig.1(a), a system with tasks of 20 ms and 400 ms periods, requiring 10 ms and 200 ms execution times, will miss deadlines on a 1 TOPS accelerator. Even increasing throughput to 10 TOPS (Fig.1(b)) without proper scheduling fails to resolve the issue. Furthermore, without a theoretical analysis, designers cannot determine whether the system after latency optimization can meet the deadline. As a result, these latency-optimized accelerators can not be safely used in time-predictable, safety-critical real-time *** address these challenges, we propose the ART framework: Accelerator Customization for Real-Time Systems. ART enables fpga accelerators to support Earliest Deadline First (EDF) scheduling and limited preemption mechanisms, specifically targeting real-time safety-critical systems. Alongside hardware support, ART provides a software framework to analyze schedulability and balance between schedulability and performance. As shown in Figure 1(c), a 1 TOPS accelerator with ART can satisfy the schedulability

关键词： fpga

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Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust Design 24

Hardcaml: An OCaml Hardware Domain-Specific Language for Eff...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Andy Ray Benjamin Devlin Fu Yong Quah Rahul Yesantharao Jane Street London United Kingdom Jane Street New York City USA

ISBN: (纸本)9798400704185

Hardcaml is an embedded hardware design domain specific language (DSL) implemented in the OCaml programming language. Unlike high level synthesis (HLS), Hardcaml allows for low level control of the underlying hardware for maximum productivity, while abstracting away many of the tedious aspects of traditional hardware definition languages (HDLs) such as Verilog or VHDL. The richness of OCaml's type system combined with Hardcaml's fast circuit elaboration checks reduces the chances of user-introduced bugs and erroneous connections with features like custom type defining, type-safe parameterized modules and elaboration-time bit-width inference and validation. Hardcaml tooling emphasizes fast feedback through simulation, testing, and verification. Hardcaml includes both a native OCaml cycle-accurate and event-driven simulator, along with backend support for external simulators such as Verilator. Unit tests can live in the source code, which can optionally include digital ASCII waveforms representing the simulator's output. Hardcaml also provides tools for SAT proving and formal verification. For several years Hardcaml has been industrially proven in many fpga designs internally in Jane Street.

关键词： cad efficiency fpga hardware domain-specific languages robustness rtl

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Towards a Machine Learning Approach to Predicting the Difficulty of fpga Routing Problems 23

Towards a Machine Learning Approach to Predicting the Diffic...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Andrew David Gunter Steven Wilton University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450394178

In this poster, we present a Machine Learning (ML) technique to predict the number of iterations needed for a Pathfinder-based fpga router to complete a routing problem. Given a placed circuit, our technique uses features gathered on each routing iteration to predict if the circuit is routable and how many more iterations will be required to successfully route the circuit. This enables early exit for routing problems which are unlikely to be completed in a target number of iterations. Such early exit may help to achieve a successful route within tractable time by allowing the user to quickly retry the circuit compilation with a different random seed, a modified circuit design, or a different fpga. We demonstrate our predictor in the VTR 8 framework; compared to VTR's predictor, our ML predictor incurs lower prediction errors on the Koios Deep Learning benchmark suite. This corresponds with an approximate time saving of 48% from early rejection of unroutable fpga designs while also successfully completing 5% more routable designs and having a 93% shorter early exit latency.

关键词： routability fpga machine learning

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