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Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of programmable Routing 20

Straight to the Point: Intra- and Intercluster LUT Connectio...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Nikolic, Stefan Zgheib, Grace Ienne, Paolo Ecole Polytech Fed Lausanne EPFL Lausanne Switzerland Intel Corp San Jose CA USA

ISBN: (纸本)9781450370998

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both within and across multiple clusters, can eschew the transistor delays of crossbars, connection blocks, and switch blocks. In this paper we investigate the usefulness of enhancing classical field-programmable gate Array (fpga) architectures with direct connections between LUTs. We present an efficient algorithm for searching automatically the most interesting patterns of such direct connections. Despite our methods being fairly conservative and relying on the use of unmodified standard CAD tools, we obtain a 2.77% improvement of the geometric mean critical path delay of a standard benchmark set, with improvement ranging from -0.17% to 7.3% for individual circuits. As modest as these results may seem at first glance, we believe that they position direct connections between LUTs as a promising topic for future research. Extending this work with dedicated CAD algorithms and exploiting the increased possibilities for optimal buffering, diagonal routing, and pipelining could prove direct connections important to the continuation of performance improvement into next generation fpgas.

关键词： intercluster architectural exploration fpga lut cluster interconnect pattern direct connection clb hardened connection search intracluster enumeration algorithm

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Graph-OPU: An fpga-Based Overlay Processor for Graph Neural Networks 23

Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural ...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Ruiqi Chen Haoyang Zhang Yuhanxiao Ma Enhao Tang Shun Li Yanxiang Zhu Jun Yu Kun Wang Fudan University Shanghai China New York University New York NY USA Fuzhou University Fuzhou China VeriMake Innovation Lab Nanjing China

ISBN: (纸本)9781450394178

Graph Neural Networks (GNNs) have outstanding performance on graph-structured data and have been extensively accelerated by field-programmable gate array (fpga) in various ways. However, existing accelerators significantly lack flexibility, especially in the following two aspects: 1) Many fpga-based accelerators only support one GNN model. 2) The processes of re-synthesizing and bitstream re-generating are very time-consuming for new GNN models. To this end, we propose a highly integrated fpga-based overlay processor for general GNN accelerations named Graph-OPU. Regarding the data structure and operation irregularity, we customize the instruction sets to support irregular operation patterns in the inference process of GNN models. Then, we customize our datapath and optimize the data format in the microarchitecture to take full advantage of high bandwidth memory (HBM). Moreover, we design the computation module to ensure a unified and fully-pipelined process of sparse matrix multiplication (SpMM) and general matrix multiplication (GEMM). Users can avoid the process of fpga reconfiguration or RTL regeneration for the newly invented GNN models. We implement the hardware prototype on Xilinx Alveo U50 and test the mainstream GNN models with 9 datasets. Graph-OPU can achieve an average of 435× and 18× speedup, while 2013× and 109× better energy efficiency, compared with the Intel I7-12700KF processor and NVIDIA RTX3090 GPU, respectively. To the best of our knowledge, Graph-OPU is the first in-depth study on fpga-based general processors for GNN acceleration with high speedup and energy efficiency.

关键词： high bandwidth memory graph neural network field-programmable gate array overlay processor

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StateMover: Combining Simulation and Hardware Execution for Efficient fpga Debugging 20

StateMover: Combining Simulation and Hardware Execution for ...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Attia, Sameh Betz, Vaughn Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450370998

Debugging consumes a large portion of fpga design time, and with the growing complexity of traditional fpga systems and the additional verification challenges posed by multiple fpgas interacting within data centers, debugging productivity is becoming even more important. Current debugging flows either depend on simulation, which is extremely slow but has full visibility, or on hardware execution, which is fast but provides very limited control and visibility. In this paper, we present StateMover, a checkpointing-based debugging framework for fpgas, which can move design state back and forth between an fpga and a simulator in a seamless way. StateMover leverages the speed of hardware execution and the full visibility and ease-of-use of a simulator. This enables a novel debugging flow that has a software-like combination of speed with full observability and controllability. StateMover adds minimal hardware to the design to safely stop the design under test so that its state can be extracted or modified in an orderly manner. The added hardware has no timing overhead and a very small area overhead. StateMover currently supports Xilinx UltraScale devices, and its underlying techniques and tools can be ported to other device families that support configuration readback. Moving the state from/to an fpga to/from a simulator can be performed in a few seconds for large fpgas, enabling a new debugging flow.

关键词： fpga Debugging Checkpointing Readback Task Interruption

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XUNI: Virtual Machine Abstraction for Self-contained and Multi-tenant Cloud fpgas 24

XUNI: Virtual Machine Abstraction for Self-contained and Mul...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Zelin Wang Guiyuan Zhu Yunhai Liu Yisong Chang Ke Zhang Mingyu Chen Institute of Computing Technology Chinese Academy of Sciences & University of Chinese Academy of Sciences Beijing China ShanghaiTech University & Institute of Computing Technology Chinese Academy of Sciences Shanghai China

ISBN: (纸本)9798400704185

fpgas have become essential infrastructural components as well as publicly rentable resources in cloud and datacenters. Although one tenant is equipped with a couple of individual physical fpga devices to solve a single problem, cloud fpgas are still underutilized in many scenarios. Considering the economic cost of such heterogeneous computing resources, it is essential to explore opportunities for fpga virtualization such that multiple tenants can share one physical device. Unlike the conventional host-centric virtualization approaches considering fpgas as I/O peripherals, we propose XUNI, an fpga-centric and self-contained virtual machine (VM) abstraction without involving the host-side virtualization techniques. Specifically, we design a hardware-software co-designed hypervisor for resource management and provisioning of various fpga VMs. First, XUNI partitions the fpga fabric into a series of reconfigurable regions that can be flexibly assembled for the deployment of large-scale designs. Second, we introduce both static partition and dynamic allocation schemes for fpga-side DRAM sharing in XUNI. Last but not least, a hierarchical multi-tenant hardware network stack is built to provide an I/O interface for each fpga VM. We implement XUNI and conduct infrastructural evaluations on a custom cloud fpga node populated with an AMD/Xilinx Zynq MPSoC chip. Preliminary results demonstrate that XUNI is capable of handling hundreds of thousands of fpga-VM-initiated memory requests per second. The hardware network stack exhibits line rate (~100Gbps) when receiving packets with the default 1500-byte MTU size. Moreover, each fpga VM boots up within hundreds of milliseconds, which is comparable to emerging lightweight host-side VMs.

关键词： fpga heterogeneous multi-tenant virtualization

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Architectural Enhancements in Intel® Agilex™ fpgas 20

Architectural Enhancements in Intel® Agilex™ FPGAs

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chromczak, Jeffrey Wheeler, Mark Chiasson, Charles How, Dana Langhammer, Martin Vanderhoek, Tim Zgheib, Grace Ganusov, Ilya Intel Corp Toronto ON Canada Intel Corp Seattle WA USA Intel Corp San Jose CA USA Intel Corp Swindon Wilts England

ISBN: (纸本)9781450370998

This paper describes architectural enhancements in Intel (R) Agilex (TM) fpgas and SoCs. Agilex devices are built on Intel's 10nm process and feature next-generation programmable fabric, tightly coupled with a quad-core ARM processor subsystem, a secure device manager, IO and memory interfaces, and multiple companion transceiver tile choices. The Agilex fabric features multiple logic block enhancements that significantly improve propagation delays and integrate more effectively with the second-generation HyperFlex (TM) pipelined routing architecture. Routing connections are re-designed to be point-to-point, dropping intermediate connections featured in prior fpga generations and replacing them with a wider variety of shorter wire types. Fine-grain programmable clock skew and time-borrowing were introduced throughout the fabric to augment the slack-balancing capabilities of HyperFlex registers. DSP capabilities are also extended to natively support new INT9/BFLOAT16/FP16 formats. Together, along with process and circuit enhancements, these changes support more than 40% performance improvement over the Stratix (R) 10 family of fpgas.

关键词： clock skew scheduling dsp routing logic module fpga

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Closing Leaks: Routing Against Crosstalk Side-Channel Attacks 20

Closing Leaks: Routing Against Crosstalk Side-Channel Attack...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Seifoori, Zeinab Mirzargar, Seyedeh Sharareh Stojilovic, Mirjana Sharif Univ Technol Tehran Iran Ecole Polytech Fed Lausanne EPFL Lausanne Switzerland

ISBN: (纸本)9781450370998

This paper presents an extension to PathFinder fpga routing algorithm, which enables it to deliver fpga designs free from risks of crosstalk attacks. Crosstalk side-channel attacks are a real threat in large designs assembled from various IPs, where some IPs are provided by trusted and some by untrusted sources. It suffices that a ring-oscillator based sensor is conveniently routed next to a signal that carries secret information (for instance, a cryptographic key), for this information to possibly get leaked. To address this security concern, we apply several different strategies and evaluate them on benchmark circuits from Verilog-to-Routing tool suite. Our experiments show that, for a quite conservative scenario where 10-20% of all design nets are carrying sensitive information, the crosstalk-attack-aware router ensures that no information leaks at a very small penalty: 1.58-7.69% increase in minimum routing channel width and 0.12-1.18% increase in critical path delay, on average. In comparison, in an AES-128 cryptographic core, less than 5% of nets carry the key or the intermediate state values of interest to an attacker, making it highly likely that the overhead for obtaining a secure design is, in practice, even smaller.

关键词： crosstalk coupling routing security fpga side-channel analysis

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Massively Simulating Adiabatic Bifurcations with fpga to Solve Combinatorial Optimization 20

Massively Simulating Adiabatic Bifurcations with FPGA to Sol...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Zou, Yu Lin, Mingjie Univ Cent Florida Orlando FL 32816 USA

ISBN: (纸本)9781450370998

Combinatorial optimizations are widely adopted in scientific and engineering applications, such as VLSI design, automated machine learning (AutoML), and compiler design. Combinatorial optimization problems are notoriously challenging to exactly solve due to the NP-hardness. Scientists have long discovered that numerically simulating classical nonlinear Hamiltonian systems can effectively solve manywell-known combinatorial optimization problems. However, such physical simulation typically requires a massive amount of computation, which even outstrips the logic capability of modern reconfigurable digital fabrics. In this work, we proposed an fpga-based general combinatorial optimization problem solver which achieved ultra-high performance and scalability. Specifically, we first reformulated a broad range of combinatorial optimization problems with a general graph-based data structure called the Ising model. Second, instead of utilizing classical simulated annealing to find an approximate solution, we utilized a new heuristic algorithm, simulated bifurcation, to search for solutions. Third, we designed an efficient hardware architecture to fully exploit fpgas' potentials to accelerate the algorithm, and proposed three hardware-software co-optimizations to further improve the performance. By experimenting on benchmarks, our proposal outperformed the state-of-the-art simulated annealing optimization solver by up to 10.91 times.

关键词： Combinatorial Optimization Physics-Inspired Computing Graph Processing Ising Model

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Efficient Neural Networks on the Edge with fpgas by Optimizing an Adaptive Activation Function 24

Efficient Neural Networks on the Edge with FPGAs by Optimizi...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Yiyue Jiang Andrius Vaicaitis John Dooley Miriam Leeser Northeastern University Boston USA Maynooth University Maynooth Ireland

ISBN: (纸本)9798400704185

The implementation of neural networks (NN) on edge devices enables local processing of wireless data but faces challenges such as high computational complexity and memory requirements when deep neural networks (DNN) are used. Shallow neural networks customized for specific problems are more efficient, requiring fewer resources, and resulting in a lower latency solution. An additional benefit of the smaller network size is that it is suitable for real-time processing on edge devices. The main concern with shallow neural networks is their accuracy performance compared to DNNs. In this paper, we demonstrate that a customized adaptive activation function (AAF) can meet the accuracy of a DNN. We designed an efficient fpga implementation for a customized segmented spline curve neural network (SSCNN) structure to replace the traditional fixed activation function with an AAF. We compared our SSCNN with different neural network structures such as real-valued time delay neural network (RVTDNN), augmented real-valued time delay neural network (ARVTDNN), and deep neural networks with different parameters. Our proposed SSCNN implementation uses 40% fewer hardware resources and no Block RAMS compared to the DNN with similar accuracy. We experimentally validate this computationally efficient and memory-saving fpga implementation of SSCNN for digital predistortion of RF power amplifiers using the AMD/Xilinx RFSoC ZCU111 while using less than 3% of the available resources, leaving space for additional real-time processing, while achieving the speed of 221 MHz.

关键词： adaptive activation function (aaf) deep learning digital predistortion fpga neural network

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Invited Tutorial: fpga Hardware Security for Datacenters and Beyond 20

Invited Tutorial: FPGA Hardware Security for Datacenters and...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Matas, Kaspar La, Tuan Grunchevski, Nikola Pham, Khoa Koch, Dirk Univ Manchester Dept Comp Sci Manchester Lancs England

ISBN: (纸本)9781450370998

Since fpgas are now available in datacenters to accelerate applications, providing fpga hardware security is a high priority. fpga security is becoming more serious with the transition to fpga-as-a-Service where users can upload their own bitstreams. Full control over fpga hardware through the bitstream enables attacks to weaken an fpga-based system. These include physically damaging the fpga equipment and leaking of sensitive information such as the secret keys of crypto algorithms. While there is no known attacks in the commercial settings so far, it is not so much a question of if but more of when? The tutorial will show concrete attacks applicable on datacenter fpgas. The goal of this tutorial is to prepare the fpga community to impending security issues in order to pave way for a proactive security. First, we will give a tour through the fpga hardware security jungle surveying practical attacks and potential threats. We will reinforce this with live demos of denial of service attacks. Less than 10% of the logic resources on an fpga can draw enough dynamic power to crash a datacenter fpga card. In the second part of the tutorial, we will show different mitigations that are either vendor supported or proposed by the academic community. In summary, the tutorial will communicate that while fpga hardware security is complicated to bring about, there are acceptable solutions for known fpga security problems.

关键词： fpga security hardware security datacenter cloud computing

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A Comprehensive Evaluation of fpga-Based Spatial Acceleration of LLMs 24

A Comprehensive Evaluation of FPGA-Based Spatial Acceleratio...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Hongzheng Chen Jiahao Zhang Yixiao Du Shaojie Xiang Zichao Yue Niansong Zhang Yaohui Cai Zhiru Zhang Cornell University Ithaca USA Tsinghua University Beijing China

ISBN: (纸本)9798400704185

Recent advancements in large language models (LLMs) have generated significant demands for efficient deployment in inference workloads. Most existing approaches rely on temporal architectures that reuse hardware units for different network layers and operators. However, these methods often encounter challenges in achieving low latency due to considerable memory access overhead. This paper investigates the feasibility and potential of model-specific spatial acceleration for LLM inference on fpgas. Our approach involves the specialization of distinct hardware units for specific operators, facilitating direct communication between them through a dataflow architecture while minimizing off-chip memory accesses. We introduce a comprehensive analytical model for estimating the performance of a spatial LLM accelerator, considering the available hardware resources on an fpga. Through our analysis, we can determine the scenarios in which fpga-based spatial acceleration can outperform its GPU-based counterpart. To enable more productive implementations of an LLM model on fpgas, we further provide a library of high-level synthesis (HLS) kernels that are composable and reusable. To validate the effectiveness of both our analytical model and HLS library, we have implemented BERT and GPT2 on an AMD Alveo U280 fpga. Experimental results demonstrate our approach can achieve up to 16.1x speedup when compared to previous fpga-based accelerators for the BERT model. For GPT generative inference, we attain a 2.2x speedup compared to DFX, an fpga overlay, in the prefill stage, while achieving a 1.9x speedup and a 5.7x improvement in energy efficiency compared to the NVIDIA A100 GPU in the decode stage.

关键词： fpga hls llm

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