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Finding and Understanding Bugs in fpga Synthesis Tools 20

Finding and Understanding Bugs in FPGA Synthesis Tools

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Herklotz, Yann Wickerson, John Imperial Coll London London England

ISBN: (纸本)9781450370998

All software ultimately relies on hardware functioning correctly. Hardware correctness is becoming increasingly important due to the growing use of custom accelerators using fpgas to speed up applications on servers. Furthermore, the increasing complexity of hardware also leads to ever more reliance on automation, meaning that the correctness of synthesis tools is vital for the reliability of the hardware. This paper aims to improve the quality of fpga synthesis tools by introducing a method to test them automatically using randomly generated, correct Verilog, and checking that the synthesised netlist is always equivalent to the original design. The main contributions of this work are twofold: firstly a method for generating random behavioural Verilog free of undefined values, and secondly a Verilog test case reducer used to locate the cause of the bug that was found. These are implemented in a tool called Verismith. This paper also provides a qualitative and quantitative analysis of the bugs found in Yosys, Vivado, XST and Quartus Prime. Every synthesis tool except Quartus Prime was found to introduce discrepancies between the netlist and the design. In addition to that, Vivado and a development version of Yosys were found to crash when given valid input. Using Verismith, eleven bugs were reported to tool vendors, of which six have already been fixed.

关键词： fuzzing logic synthesis Verilog test case reduction

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GraphACT: Accelerating GCN Training on CPU-fpga Heterogeneous Platforms 20

GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneou...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Zeng, Hanqing Prasanna, Viktor Univ Southern Calif Los Angeles CA 90007 USA

ISBN: (纸本)9781450370998

Graph Convolutional Networks (GCNs) have emerged as the state-of-the-art deep learning model for representation learning on graphs. It is challenging to accelerate training of GCNs, due to (1) substantial and irregular data communication to propagate information within the graph, and (2) intensive computation to propagate information along the neural network layers. To address these challenges, we design a novel accelerator for training GCNs on CPU-fpga heterogeneous systems, by incorporating multiple algorithm-architecture co-optimizations. We first analyze the computation and communication characteristics of various GCN training algorithms, and select a subgraph-based algorithm that is well suited for hardware execution. To optimize the feature propagation within subgraphs, we propose a light-weight pre-processing step based on a graph theoretic approach. Such pre-processing performed on the CPU significantly reduces the memory access requirements and the computation to be performed on the fpga. To accelerate the weight update in GCN layers, we propose a systolic array based design for efficient parallelization. We integrate the above optimizations into a complete hardware pipeline, and analyze its load-balance and resource utilization by accurate performance modeling. We evaluate our design on a Xilinx Alveo U200 board hosted by a 40-core Xeon server. On three large graphs, we achieve an order of magnitude training speedup with negligible accuracy loss, compared with state-of-the-art implementation on a multi-core platform.

关键词： fpga graph convolutional network heterogeneous computing

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Using OpenCL to Enable Software-like Development of an fpga-Accelerated Biophotonic Cancer Treatment Simulator 20

Using OpenCL to Enable Software-like Development of an FPGA-...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Young-Schultz, Tanner Lilge, Lothar Brown, Stephen Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Princess Margaret Canc Ctr Toronto ON Canada Univ Toronto Dept Med Biophys Toronto ON Canada

ISBN: (纸本)9781450370998

The simulation of light propagation through tissues is important for medical applications, such as photodynamic therapy (PDT) for cancer treatment. To optimize PDT an inverse problem, which works backwards from a desired distribution of light to the parameters that caused it, must be solved. These problems have no closed-form solution and therefore must be solved numerically using an iterative method. This involves running many forward light propagation simulations which is time-consuming and computationally intensive. Currently, the fastest general software solver for this problem is FulMonteSW. It models complex 3D geometries with tetrahedral meshes and uses Monte Carlo techniques to model photon interactions with tissues. This work presents FullMontefpgaCL: an fpga-accelerated version of FullMonteSW using an Intel Stratix 10 fpga and the Intel fpga SDK for OpenCL. FullMontefpgaCL has been validated and benchmarked using several models and achieves improvements in performance (4x) and energy-efficiency (11x) over the optimized and multi-threaded FullMonteSW implementation. We discuss methods for extending the design to improve the performance and energy-efficiency ratios to 16x and 17x, respectively. We achieved these gains by developing in an agile fashion using OpenCL to facilitate quick prototyping and hardware-software partitioning. However, achieving competitive area and performance required careful design of the hardware pipeline and expression of its structure in OpenCL. This led to a hybrid design style that can improve productivity when developing complex applications on an fpga.

关键词： Biophotonics simulation Monte Carlo acceleration fpga OpenCL

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LUXOR: An fpga logic cell architecture for eficient compressor tree implementations

LUXOR: An FPGA logic cell architecture for eficient compress...

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2020 acm/sigda international symposium on field-programmable gate arrays, fpga 2020

作者： Rasoulinezhad, Seyed Ramin Siddhartha Zhou, Hao Wang, Lingli Boland, David Leong, Philip H.W. School of Electrical and Information Engineering University of Sydney Sydney2006 Australia State Key Lab of ASIC and System Fudan University Shanghai201203 China

ISBN: (纸本)9781450370998

We propose two tiers of modiications to fpga logic cell architecture to deliver a variety of performance and utilization beneits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-speciic modiications to both Xilinx and Intel fpgas, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modiications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13-19% in logic utilization on micro-benchmarks from a variety of *** benchmarks beneit the most with an average reduction of 37-47% in logic utilization, which is due to the highly-eicient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells. © 2020 Association for Computing Machinery.

关键词： field programmable gate arrays (fpga)

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fpga-Accelerated Samplesort for Large Data Sets 20

FPGA-Accelerated Samplesort for Large Data Sets

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chen, Han Madaminov, Sergey Ferdman, Michael Milder, Peter SUNY Stony Brook Stony Brook NY 11794 USA

ISBN: (纸本)9781450370998

Sorting is a fundamental operation in many applications such as databases, search, and social networks. Although fpgas have been shown very effective at sorting data sizes that fit on chip, systems that sort larger data sets by shuffling data on and off chip are bottlenecked by costly merge operations or data transfer time. We propose a new technique for sorting large data sets, which uses a variant of the samplesort algorithm on a server with a PCIe-connected fpga. Samplesort avoids merging by randomly sampling values to determine how to partition data into non-overlapping buckets that can be independently sorted. The key to our design is a novel parallel multi-stage hardware partitioner, which is a scalable high-throughput solution that greatly accelerates the samplesort partitioning step. Using samplesort for fpga-accelerated sorting provides several advantages over mergesort, while also presenting a number of new challenges that we address with cooperation between the fpga and the software running on the host CPU. We prototype our design using Amazon Web Services fpga instances, which pair a Xilinx Virtex UltraScale+ fpga with a high-performance server. Our experiments demonstrate that our prototype system sorts 230 key-value records with a speed of 7.2 GB/s, limited only by the on-board DRAM capacity and available PCIe bandwidth. When sorting 230 records, our system exhibits a 37.4x speedup over the widely used GNU parallel sort on an 8-thread state-of-the-art CPU.

关键词： sorting samplesort partitioning fpga

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Real-Time Spatial 3D Audio Synthesis on fpgas for Blind Sailing 20

Real-Time Spatial 3D Audio Synthesis on FPGAs for Blind Sail...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Singhani, Anish Morrow, Alexander Olin Coll Engn Needham MA 02492 USA

ISBN: (纸本)9781450370998

The real-time synthesis of 3D spatial audio has many applications, from virtual reality to navigation for the visually-impaired. Head-related transfer functions (HRTF) can be used to generate spatial audio based on a model of the user's head. Previous studies have focused on the creation and interpolation of these functions with little regard for real-time performance. In this paper, we present an fpga-based platform for real-time synthesis of spatial audio using FIR filters created from head-related transfer functions. For performance reasons, we run filtering, crossfading, and audio output on fpga fabric, while calculating audio source locations and storing audio files on the CPU. We use a head-mounted 9-axis IMU to track the user's head in real-time and adjust relative spatial audio locations to create the perception that audio sources are fixed in space. Our system, running on a Xilinx Zynq Z-7020, is able to support 4X more audio sources than a comparable GPU and 8X more sources than a CPU while maintaining sub-millisecond latency and comparable power consumption. Furthermore, we show how our system can be leveraged to communicate the location of landmarks and obstacles to a visually-impaired user during a sailing race or other navigation scenario. We test our system with multiple users and show that, as a result of our reduced latency, a user is able to locate a virtual audio source with an extremely high degree of accuracy and navigate toward it.

关键词： fpga Spatial Audio HRTF Real-Time DSP Blind Sailing

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HMLib: Efficient Data Transfer for HLS Using Host Memory 23

HMLib: Efficient Data Transfer for HLS Using Host Memory

引用

Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Michael Lo Young-kyu Choi Weikang Qiao Mau-Chung Frank Chang Jason Cong University of California Los Angeles Los Angeles CA USA Inha University Incheon Republic of Korea

ISBN: (纸本)9781450394178

Streaming applications compose an important portion of the workloads that fpgas may accelerate but suffer from inefficient data movement. The inefficiency stems from copying data indirectly into the fpga DRAM rather than directly into its on-chip memory, substantially diminishing the end-to-end speedup, especially for small workloads (hundreds of kilobytes). AMD Xilinx's Host Memory IP (HMI) aims to address the data movement problem by exposing to the developer an High-Level Synthesis (HLS) interface that moves the data from the host directly to the fpga's on-chip memory. However, using HMI purely for its interface without additional code changes incurred a 3.3x slowdown in comparison with the current programming model. The slowdown mainly originates from OpenCL call overhead and the kernel control logic unnecessarily switching states. To overcome these issues, we propose Host Memory Library (HMLib), an efficient HLS-based library that facilitates data transfer on behalf of the user. HMLib not only optimizes the runtime stack for efficient data transfer, but also provides HLS compatible and user-friendly interfaces. We demonstrate HMLib's effectiveness for streaming applications (Deflate compression and CRC32) with improvements of up to up to 36.2X over OpenCL-DDR and up to 79.5X over raw HMI for small-scale data while maintaining little-to-no performance loss for large scale inputs. We plan to open source our work in the future.

关键词： high-level synthesis field-programmable gate array on-chip memory host memory opencl streaming workload

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A Flexible Toolflow for Mapping CNN Models to High Performance fpga-based Accelerators 23

A Flexible Toolflow for Mapping CNN Models to High Performan...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Yongzheng Chen Gang Wu Northeastern University Shenyang China

ISBN: (纸本)9781450394178

There have been many studies on developing automatic tools for mapping CNN models onto fpgas. However, challenges remain in designing an easy-to-use toolflow. First, the toolflow should be able to handle models exported from various deep learning frameworks and models with different topologies. Second, the hardware architecture should make better use of on-chip resources to achieve high performance. In this work, we build a toolflow upon Open Neural Network Exchange (ONNX) IR to support different DL frameworks. We also try to maximize the overall throughput via multiple hardware-level efforts. We propose to accelerate the convolution operation by applying parallelism not only at the input and output channel level, but also at the output feature map level. Several on-chip buffers and corresponding management algorithms are also designed to leverage abundant memory resources. Moreover, we employ a fully pipelined systolic array running at 400 MHz as the convolution engine, and develop a dedicated bus to implement the im2col algorithm and provide feature inputs to the systolic array. We generated 4 accelerators with different systolic array shapes and compiled 12 CNN models for each accelerator. Deployed on a Xilinx VCU118 evaluation board, the performance of convolutional layers can reach 3267.61 GOPS, which is 99.72% of the ideal throughput (3276.8 GOPS). We also achieve an overall throughput of up to 2424.73 GOPS. Compared with previous studies, our toolflow is more user-friendly. The end-to-end performance of the generated accelerators is also better than that of related work at the same DSP utilization.

关键词： field-programmable gate array (fpga) toolflow convolutional neural network (CNN) systolic array memory management

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AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture 23

AoCStream: All-on-Chip CNN Accelerator With Stream-Based Lin...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Hyeong-Ju Kang Korea University of Technology and Education Cheonan-si South Korea

ISBN: (纸本)9781450394178

Convolutional neural network (CNN) accelerators are being widely used for their efficiency, but they require a large amount of memory, leading to the use of slow and power consuming external memories. This paper exploits two schemes to reduce the required memory amount and ultimately to implement a CNN of reasonable performance only with on-chip memory of a practical device like a low-end fpga. To reduce the memory amount of the intermediate data, a stream-based line-buffer architecture and a dataflow for the architecture are proposed instead of the conventional frame-based architecture, where the amount of the intermediate data memory is proportional to the square of the input image size. The architecture consists of layer-dedicated blocks operating in a pipelined way with the input and output streams. Each convolutional layer block has a line buffer storing just a few rows of input data. The sizes of the line buffers are proportional to the width of the input image, so the architecture requires less intermediate data storage, especially in the trend of getting larger input size in modern object detection CNNs. In addition, the weight memory is reduced by the accelerator-aware pruning. The experimental results show that a whole object detection CNN can be implemented even on a low-end fpga without an external memory. Compared to previous accelerators with similar object detection accuracy, the proposed accelerator reaches higher throughput even with less fpga resources of LUTs, registers, and DSPs, showing higher efficiency.

关键词： fpga cnn accelerator on-chip memory object detection

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fpga-based Trainable Autoencoder for Communication Systems 22

FPGA-based Trainable Autoencoder for Communication Systems

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Proceedings of the 2022 acm/sigda international symposium on field-programmable gate arrays

作者： Jonas Ney Sebastian Dörner Matthias Herrmann Mohammad Hassani Sadi Jannis Clausius Stephan ten Brink Norbert Wehn TU Kaiserslautern Kaiserslautern Germany University of Stuttgart Stuttgart Germany

ISBN: (纸本)9781450391498

In communication systems, autoencoder refers to a system that replaces parts of the traditional transmitter and receiver of the baseband processing chain with artificial neural networks (ANNs). This allows to jointly train the system for an underlying channel model by reconstructing the input symbols at the output. Since the actual behavior of a real communication channel cannot be perfectly reproduced by an abstract model, it is necessary for the autoencoder to adapt to the changing conditions at runtime. Thus, online fine-tuning, in the form of ANN-retraining is of great importance. A platform able to satisfy the low-latency and low-power requirements of embedded communication systems are field-programmable gate arrays (fpgas). In this paper, we present an online-trainable low-power fpga architecture for the receiver of an autoencoder-based communication chain. The architecture is embedded into an exploration framework that automatically determines the optimal degree of parallelism to minimize latency or power consumption. Our solutions achieve 2000×higher throughput than a high-performance GPU, draw 5×less power than an embedded CPU and are 5800×more energy efficient compared to an embedded GPU, for a batch size of one. To the best of our knowledge, this is the first fpga-based autoencoder implementation for communication systems.

关键词： backpropagation autoencoder fpga ann communication

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