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Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach 24

Automatic Hardware Pragma Insertion in High-Level Synthesis:...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Stéphane Pouget Louis-Noël Pouchet Jason Cong University of California Los Angeles Los Angeles CA USA Colorado State University Fort Collins CO USA

ISBN: (纸本)9798400704185

High-Level Synthesis enables the rapid prototyping of hardware accelerators, by combining a high-level description of the functional behavior of a kernel with a set of micro-architecture optimizations as inputs. Such pragmas may describe the pipelining and replication of units, or even higher-level transformations for HLS such as automatic data caching using the AMD/Xilinx Merlin compiler. Selecting the best combination of pragmas, even within a restricted set, remains particularly challenging and the typical state-of-practice uses design-space exploration to navigate this space. But due to the highly irregular performance distribution of pragma configurations, typical DSE approaches are either extremely time consuming, or operating on a severely restricted search space. In this work we propose a framework to automatically insert HLS pragmas in regular loop-based programs, supporting pipelining, unit replication (coarse- and fine-grain), and data caching. We develop a simple analytical performance and resource model as a function of the input program properties and pragmas inserted. We prove this model provides a lower bound on the actual performance for any possible configuration. We then encode this model as a Non-Linear Program, by making the pragma configuration as unknowns of the system, which is computed optimally by solving this NLP. This approach can also be used during DSE, to quickly prune points with a (possibly partial) pragma configuration, employing this latency lower bound property. We extensively evaluate our end-to-end fully implemented system, showing it can effectively manipulate spaces of billions of designs in seconds to minutes for the kernels evaluated.

关键词： fpga hls non-linear programming program optimization

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End-to-End Optimization of Deep Learning Applications 20

End-to-End Optimization of Deep Learning Applications

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Sohrabizadeh, Atefeh Wang, Jie Cong, Jason Univ Calif Los Angeles Los Angeles CA 90095 USA

ISBN: (纸本)9781450370998

The irregularity of recent Convolutional Neural Network (CNN) models such as less data reuse and parallelism due to the extensive network pruning and simplification creates new challenges for fpga acceleration. Furthermore, without proper optimization, there could be significant overheads when integrating fpgas into existing machine learning frameworks like TensorFlow. Such a problem is mostly overlooked by previous studies. However, our study shows that a naive fpga integration into TensorFlow could lead to up to 8.45x performance degradation. To address the challenges mentioned above, we propose several SW/HW co-design approaches to perform the end-to-end optimization of deep learning applications. We present a flexible and composable architecture called FlexCNN. It can deliver high computation efficiency for different types of convolution layers using techniques including dynamic tiling and data layout optimization. FlexCNN is further integrated into the TensorFlow framework with a fully-pipelined software-hardware integration flow. This alleviates the high overheads of TensorFlow-fpga handshake and other non-CNN processing stages. We use OpenPose, a popular CNN-based application for human pose recognition, as a case study. Experimental results show that with the FlexCNN architecture optimizations, we can achieve 2.3x performance improvement. The pipelined integration stack leads to a further 5x speedup. Overall, the SW/HW co-optimization produces a speedup of 11.5x and results in an end-to-end performance of 23.8FPS for OpenPose with floating-point precision, which is the highest performance reported for this application on fpga in the literature.

关键词： fpga CNN OpenPose TensorFlow tiling integration

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fpga Acceleration for Successive Interference Cancellation in Severe Multipath Acoustic Communication Channels 23

FPGA Acceleration for Successive Interference Cancellation i...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Jinfeng Li Yahong Rosa Zheng Lehigh University Bethlehem PA USA

ISBN: (纸本)9781450394178

This paper proposes a hardware implementation of a Successive Interference Cancellation (SIC) scheme in a Turbo Equalizer for very long multipath fading channels where the Intersymbol-interference (ISI) channel length L is on the order of 100 taps. To reduce the computational complexity caused by large matrix arithmetic in the SIC, we explore the data dependencies and convolutional nature of the SIC algorithm and propose an fpga acceleration architecture by taking advantage of the high degree of parallelism and the flexible data movements offered by fpga. Instead of reconstructing interference in symbol-wise by matrix and vector multiplication directly for each symbol in a block, we propose a two-stage processing algorithm. The first stage is block-wise processing, where the convolution of the channel impulse response (CIR) vector and the vector consisting of the whole symbol block is computed. The second stage is symbol-wise processing but turns to the multiplication of one symbol and the CIR vector. The result shows that for a block of Nblk symbols and a channel of length L, the proposed architecture completes the SIC within 2Nblk+L clock cycles, while direct matrix multiplication requires L×Nblk clock cycles. Implemented on a Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit, the SIC and equalization in one turbo iteration based on this architecture is completed around 40 us for a 1024 symbol block and a channel length of L=100. This architecture achieves around 40× speed-up compared with the implementation on a powerful CPU platform.

关键词： convolution matrix arithmetic SIC turbo equalizer two-stage

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When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network 20

When Massive GPU Parallelism Ain't Enough: A Novel Hardware ...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Rybalkin, Vladimir Wehn, Norbert Univ Kaiserslautern Microelect Syst Design Res Grp Kaiserslautern Germany

ISBN: (纸本)9781450370998

Multidimensional Long Short-Term Memory (MD-LSTM) neural network is an extension of one-dimensional LSTM for data with more than one dimension that allows MD-LSTM to show state-of-the-art results in various applications including handwritten text recognition, medical imaging, and many more. However, efficient implementation suffers from very sequential execution that tremendously slows down both training and inference compared to other neural networks. This is the primary reason that prevents intensive research involving MD-LSTM in the recent years, despite large progress in microelectronics and architectures. The main goal of the current research is to provide acceleration for inference of MD-LSTM, so to open a door for efficient training that can boost application of MD-LSTM. By this research we advocate that fpga is an alternative platform for deep learning that can offer a solution in cases when a massive parallelism of GPUs does not provide the necessary performance required by the application. In this paper, we present the first hardware architecture for MD-LSTM. We conduct a systematic exploration of precision vs. accuracy trade-off using challenging dataset for historical document image binarization from DIBCO 2017 contest, and well known MNIST dataset for handwritten digits recognition. Based on our new architecture we implement fpga-based accelerator that outperforms NVIDIA K80 GPU implementation in terms of runtime by up to 50x and energy efficiency by up to 746x. At the same time, our accelerator demonstrates higher accuracy and comparable throughput in comparison with state-of-the-art fpga-based implementations of multilayer perceptron for MNIST dataset.

关键词： Long Short-Term Memory LSTM MD-LSTM 2D-LSTM fpga MNIST DIBCO Zynq Image Binarization Hardware Architecture Deep Learning

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Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial fpga Routing 23

Mitigating the Last-Mile Bottleneck: A Two-Step Approach For...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Shashwat Shrivastava Stefan Nikolic Chirag Ravishankar Dinesh Gaitonde Mirjana Stojilovic EPFL Lausanne Switzerland AMD Longmont CO USA AMD San Jose CA USA

ISBN: (纸本)9781450394178

We identified that in modern commercial fpgas, routing signals from the general interconnect to the inputs of the CLB primitives through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic research often neglecting the runtime of last-mile routing through the IIB. We propose a two-step routing approach that allows resolving this bottleneck by leveraging massive parallelism of today's compute infrastructure. The main premise that enables massive parallelization is that once the signals are legally routed in the general interconnect-only reaching the inputs of the IIB, but not the final targets-the remaining last-mile routing through the IIB can be completed independently for each fpga *** ran experiments using ISPD16 and industrial designs to demonstrate the dominant contribution of last-mile routing to the router's runtime. We used an architectural model closely resembling Xilinx UltraScale fpgas, which makes it highly representative of the current state of the art. For ISPD16 benchmarks, we observed that when the router is instructed to complete the entire routing, including its last-mile portion, the average number of heap pushes (a machine-agnostic measure of runtime) increases 4.1× compared to a simplified reference in which last-mile routing is neglected. On industrial designs, the number of heap pushes increased 4.4×. Last-mile routing was successfully completed using a SAT-based router in up to 83% of fpga tiles. With a slight increase in density of IIB connectivity, we were able to bring the completion success rate up to 100%.

关键词： fpga parallel routing

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Single-Batch CNN Training using Block Minifloats on fpgas 23

Single-Batch CNN Training using Block Minifloats on FPGAs

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Chuliang Guo Binglei Lou Xueyuan Liu David Boland Philip H.W. Leong The University of Sydney Sydney NSW Australia

ISBN: (纸本)9781450394178

Training convolutional neural networks remains a challenge on resource-limited edge devices due to its intensive computations, large storage requirements, and high bandwidth. Error back-propagation, gradient generation, and weight update usually require high precision to guarantee model accuracy, which places a further burden on computation and bandwidth. This paper presents the first parallel fpga CNN training accelerator with block minifloat datatypes. We first propose a heuristic bit-width allocation technique to derive a unified 8-bit block minifloat format with a sign bit, 2 exponent bits, and 5 mantissa bits. In contrast to previous techniques, the same data format is used for weights, activations, errors, and gradients. Using this format, accuracy similar to 32-bit single precision floating point is achieved and thus simplifies the fpga-based designs of computational units such as multiply-and-add. In addition, we propose a unified Conv block to deal with Conv and transposed Conv in the forward and backward paths respectively; and a dilated Conv block with a weight kernel partition scheme for gradient generation. Both Conv blocks support non-unit stride, this being crucial for the residual connections that appear in modern CNNs. For training of ResNet20 on the CIFAR-10 dataset with a batch size of 1, our accelerator on a Xilinx Ultrascale+ ZCU102 fpga achieves state-of-the-art single-batch throughput of 144.64 and 192.68 GOPs with and without batch normalisation layers respectively.

关键词： convolutional neural networks HLS fpga acceleration deep learning

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Nimblock: Scheduling for Fine-grained fpga Sharing through Virtualization 23

Nimblock: Scheduling for Fine-grained FPGA Sharing through V...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Meghna Mandava Deming Chen University of Illinois Urbana-Champaign Urbana IL USA

ISBN: (纸本)9781450394178

As fpgas become ubiquitous compute platforms, existing research has focused on enabling virtualization features to facilitate fine-grained fpga sharing. We employ an overlay architecture which enables arbitrary, independent user logic to share portions of a single fpga by dividing the fpga into independently reconfigurable slots. We then explore scheduling possibilities to effectively time- and space-multiplex the virtualized fpga by introducing Nimblock. The Nimblock scheduling algorithm balances application priorities and performance degradation to improve response time and reduce deadline violations. Unlike other algorithms, Nimblock explores both preemption and pipelining as a scheduling parameter to dynamically change resource allocations, and automatically allocates resources to enable suitable parallelism for an application without additional user input. We demonstrate system feasibility by realizing the complete system on a Xilinx ZCU106 fpga. We evaluate our algorithm and validate its efficacy by measuring results from real workloads running on the board with different real-time constraints and priority levels. In our exploration, we compare our novel Nimblock algorithm against a no-sharing and no-virtualization baseline algorithm and three other algorithms which support sharing and virtualization. We achieve up to 5x lower average response time when compared to the baseline algorithm and up to 2.1x average response time improvement over competitive scheduling algorithms that support sharing within our virtualization environment. We additionally demonstrate up to 49% fewer deadline violations and up to 2.6x lower tail response times when compared to other high-performance algorithms.

关键词： overlay architectures fpga virtualization reconfigurable computing real-time scheduling

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Thermal and Voltage Side and Covert Channels and Attacks in Cloud fpgas 20

Thermal and Voltage Side and Covert Channels and Attacks in ...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Szefer, Jakub Yale Univ New Haven CT 06511 USA

ISBN: (纸本)9781450370998

Cloud fpgas have been gaining interest in recent years due to the ability of users to request fpga resources quickly, flexibly, and on-demand. In addition to the existing single-tenant deployments, where each user gets an access to a whole fpga, recent academic proposals have looked at creating multi-tenant deployments, where multiple users share a single fpga, e.g., [3]. In both settings, there is a large amount of infrastructure and physical resources that are shared among users. Sharing of the physical resources in data centers and processors is well known to lead to potential attacks, e.g., [4]. However, only recently have there been demonstrations of various security attacks that our group and others have shown to be possible in Cloud fpga setting, e.g., [5]. This talk will discuss Cloud fpga security from the perspective of side and covert channel attacks that arise due to these shared resources. It will first cover our recent work on thermal channels that can be used to create covert channels between users renting same fpga over time [5]. These channels can create stealthy communication medium for leaking small amounts of sensitive information, e.g., cryptographic keys. As defense strategies, the talk will point out possible solutions at the system level and at the hardware level. At the system level, adding delays between when different users can access the same fpga, or preventing users from being able to identify unique fpga instances can mitigate the threats, but does increase overhead. At the hardware level, additional cooling to erase thermal information after users uses and fpga, or new sensors to monitor fpgas and generate an alert when excessive heat is detected are possible solutions that will be discussed. The talk will also discuss recent work on voltage-based attacks that leverage custom circuits instantiated inside the fpgas to measure voltage changes. Voltage-based channels can be used to leak sensitive information across fpgas (in single-tenan

关键词： fpga security Cloud computing Side and covert channels

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Dependency-Driven Trace-Based Network-on-Chip Emulation on fpgas 20

Dependency-Driven Trace-Based Network-on-Chip Emulation on F...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Thiem Van Chu Kise, Kenji Tanaka, Kiyofumi Japan Adv Inst Sci & Technol Tokyo Japan Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9781450370998

fpga emulation is a promising approach to accelerating Network-on-Chip (NoC) modeling which has traditionally relied on software simulators. In most early studies of fpga-based NoC emulators, only synthetic workloads like uniform and bit permutations were considered. Although a set of carefully designed synthetic workloads can reveal a relatively thorough coverage of the characteristics of the NoC under evaluation, they alone are insufficient, especially when the NoC needs to be optimized for specific applications. In such cases, trace-driven workloads are effective. However, there is a problem with conventional trace-driven workloads that has been pointed out by some recent studies: the network load and congestion may be distorted because dependencies between packets are not considered. These studies also provide infrastructures for extending existing software simulators to enforce dependencies between packets. Unfortunately, enforcing dependencies between packets is not trivial in the fpga emulation approach. Therefore, although there are some recent fpga-based NoC emulators supporting trace-driven workloads, most of them ignore packet dependencies. In this paper, we first clarify the challenges of supporting trace-driven workloads with dependencies between packets taken into account in the fpga emulation approach. We then propose efficient methods and architectures to tackle these challenges and build an fpga-based NoC emulator, which we call DNoC, based on the proposals. Our evaluation results show that (1) on a VC707 fpga board, DNoC achieves an average speed of 10,753K cycles/s when emulating an 8x8 NoC with trace data collected from full-system simulation of the PARSEC benchmark suite, which is 274x higher than the speed reported in a recent related work on dependency-driven trace-based NoC emulation on fpgas;(2) Compared to BookSim, one of the most popular NoC simulators, DNoC is 395x faster while providing the same results;(3) DNoC can scale to a 4,096-node

关键词： fpga network-on-chip trace-driven emulation dependency

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Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based fpga Platforms 23

Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming o...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Kaveh Aasaraai Emanuele Cesena Rahul Maganti Nicolas Stalder Javier Varela Kevin Bowers Jump Trading Chicago IL USA Jump Crypto San Francisco CA USA Jump Crypto Chicago IL USA Jump Crypto Zurich Switzerland

ISBN: (纸本)9781450394178

Number-Theoretic-Transform (NTT) is a variation of Fast-Fourier-Transform (FFT) on finite fields. NTT is being increasingly used in blockchain and zero-knowledge proof applications. Although FFT and NTT are widely studied for fpga implementation, we believe CycloneNTT is the first to solve this problem for large data sets (2^24, 64-bit numbers) that would not fit in the on-chip RAM. CycloneNTT uses a state-of-the-art butterfly network and maps the dataflow to hybrid FIFOs composed of on-chip SRAM and external memory. This manifests into a quasi-streaming data access pattern minimizing external memory access latency and maximizing throughput. We implement two variants of CycloneNTT optimized for DDR and HBM external memories. Although historically this problem has been shown to be memory-bound, CycloneNTT's quasi-streaming access pattern is optimized to the point that when using HBM (Xilinx C1100), the architecture becomes compute-bound. On the DDR-based platform (AWS F1), the latency of the application is equal to the streaming of the entire dataset log(N) times to/from external memory. Moreover, exploiting HBM's larger number of channels, and following a series of additional optimizations, CycloneNTT only requires log(N)/6 passes.

关键词： zero-knowledge ntt

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