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检索条件"任意字段=ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004"

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A Novel fpga Simulator Accelerating Reinforcement Learning-Based Design of Power Converters 23

A Novel FPGA Simulator Accelerating Reinforcement Learning-B...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Zhenyu Xu Miaoxiang Yu Qing Yang Yeonho Jeong Tao Wei The University of Rhode Island Kingston RI USA

ISBN: (纸本)9781450394178

High-efficiency energy conversion systems have become increasingly important due to their wide use in all electronic systems such as data centers, smart mobile devices, E-vehicles, medical instruments, and so forth. Complex and interdependent parameters make optimal designs of power converters challenging to get. Recent research has shown that reinforcement learning (RL) shows great promise in the design of such converter circuits. A trained RL agent can search for optimal design parameters for power conversion circuit topologies under targeted application requirements. Training an RL agent requires numerous circuit simulations. As a result, they may take days to complete, primarily because of the slow time-domain circuit *** abstract proposes a new fpga architecture that accelerates the circuit simulation and hence substantially speeds up the RL-based design method for power converters. Our new architecture supports all power electronic circuit converters and their variations. It substantially improves the training speed of RL-based design methods. High-level synthesis (HLS) was used to build the accelerator on Amazon Web Service (AWS) F1 instance. An AWS virtual PC hosts the training algorithm. The host interacts with the fpga accelerator by updating the circuit parameters, initiating simulation, and collecting the simulation results during training iterations. A script was created on the host side to facilitate this design method to convert a netlist containing circuit topology and parameters into core matrices in the fpga accelerator. Experimental results showed 60x overall speedup of our RL-based design method in comparison with using a popular commercial simulator, PowerSim.

关键词： power electronics simulation fpga accelerator reinforcement learning

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Multi-tenant fpga Security: Challenges and Opportunities 20

Multi-tenant FPGA Security: Challenges and Opportunities

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Koeberl, Patrick Intel Labs Hillsboro OR 97124 USA

ISBN: (纸本)9781450370998

An emerging trend in the data center is the at-scale deployment of field-programmable gate arrays (fpgas) which combine multi-gigabit and ultra-low latency workload acceleration with hardware-level reconfigurability. In particular, for applications such as Deep Learning where techniques and algorithms are rapidly changing, the inherent flexibility of fpgas grants them an edge over hardened data processing units such as ASICs or GPUs. Inevitably, Cloud Service Providers (CSPs) will seek to maximize resource utilization for their fpga investments as they currently do for general-purpose computing resources. Current fpga deployments in the data center tend to be single-tenant or support multiple tenants through time multiplexing (temporal multi-tenancy) which can result in resource underutilization. This approach does not scale and presents challenges for elastic workloads whose properties are not fully known ahead of time. Instead, we expect that closing the resource utilization gap will require efficient spatial allocation of fpga resources across multiple tenants while maintaining security and QoS guarantees. In particular, new usage models such as fpga-as-a-Service, where resources are exposed directly to the cloud tenant, present unique challenges on the security and QoS side. In this talk we review the threat landscape and trust models associated with fpga multi-tenancy, highlight future research challenges and examine the unique opportunities that fpga multi-tenancy enables given adequate guarantees on security and QoS.

关键词： fpga cloud computing data center hardware acceleration multi-tenancy security deep learning

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Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation 23

Janus: An Experimental Reconfigurable SmartNIC with P4 Progr...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Bharat Sukhwani Mohit Kapur Alda Ohmacht Liran Schour Martin Ohmacht Chris Ward Chuck Haymes Sameh Asaad IBM Research Yorktown Hts. NY USA IBM Research Haifa Israel IBM Research Hursley United Kingdom

ISBN: (纸本)9781450394178

Disparate deployment models of cloud computing pose varying requirements on cloud infrastructure components such as networking, storage, provisioning, and security. Infrastructure providers need to study these and often create custom infrastructure components to satisfy these requirements. A major challenge in the research and development of these cloud infrastructure solutions, however, is the availability of customizable platforms for experimentation and trade-off analysis of the various hardware and software components. Most platforms are either general purpose or bespoke solutions created to assist a particular task, too rigid to allow meaningful customization. In this work, we present a 100G reconfigurable smartNIC prototyping platform called Janus that enables cloud infrastructure research and hardware-software co-design of infrastructure components such as hypervisor, secure boot, software defined networking and distributed storage. The platform provides a path to optimize the stack by offloading the functionalities from the host x86 to the embedded processor on the smartNIC and optimize performance by moving pieces to hardware using P4. Further, our platform provides hardware-enforced isolation of cloud network control plane, thereby securing the control plane from the tenants even for bare-metal deployments.

关键词： fpga cloud infrastructure smartnic sdn isolation p4 networking

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Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on fpgas 20

Boyi: A Systematic Framework for Automatically Deciding the ...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Jiang, Jiantong Wang, Zeke Liu, Xue Gomez-Luna, Juan Guan, Nan Deng, Qingxu Zhang, Wei Mutlu, Onur Northeastern Univ Dept Comp Sci & Engn Boston MA 02115 USA Swiss Fed Inst Technol Zurich Switzerland Hong Kong Polytech Univ Dept Comp Hong Kong Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China

ISBN: (纸本)9781450370998

fpga vendors provide OpenCL software development kits for easier programmability, with the goal of replacing the time-consuming and error-prone register-transfer level (RTL) programming. Many studies explore optimization methods (e.g., loop unrolling, local memory) to accelerate OpenCL programs running on fpgas. These programs typically follow the default OpenCL execution model, where a kernel deploys multiple work-items arranged into work-groups. However, the default execution model is not always a good fit for an application mapped to the fpga architecture, which is very different from the multithreaded architecture of GPUs, for which OpenCL was originally designed. In this work, we identify three other execution models that can better utilize the fpga resources for the OpenCL applications that do not fit well into the default execution model. These three execution models are based on two OpenCL features devised for fpga programming (namely, single work-item kernel and OpenCL channel). We observe that the selection of the right execution model determines the performance upper bound of a particular application, which can vary by two orders magnitude between the most suitable execution model and the most unsuitable one. However, there is no way to select the most suitable execution model other than empirically exploring the optimization space for the four of them, which can be prohibitive. To help fpga programmers identify the right execution model, we propose Boyi, a systematic framework that makes automatic decisions by analyzing OpenCL programming patterns in an application. After finding the right execution model with the help of Boyi, programmers can apply other conventional optimizations to reach the performance upper bound. Our experimental evaluation shows that Boyi can 1) accurately determine the right execution model, and 2) greatly reduce the exploration space of conventional optimization methods.

关键词： fpga OpenCL Execution Model Programmability

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Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme 23

Multi-bit-width CNN Accelerator with Systolic-in-Systolic Da...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Mingqiang Huang Yucen Liu Sixiao Huang Kai Li Qiuping Wu Hao Yu Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China Southern University of Science and Technology Shenzhen China

ISBN: (纸本)9781450394178

Multi-bit-width neural network enlightens a promising method for high performance yet energy efficient edge computing due to its balance between software algorithm accuracy and hardware efficiency. To date, fpga has been one of the core hardware platforms for deploying various neural networks. However, it is still difficult to fully make use of the dedicated digital signal processing (DSP) blocks in fpga for accelerating the multi-bit-width network. In this work, we develop state-of-the-art multi-bit-width convolutional neural network accelerator with novel systolic-in-systolic type of dataflow and single DSP multiple multiplication (SDMM) INT2/4/8 execution scheme. Multi-level optimizations have also been adopted to further improve the performance, including group-vector systolic array for maximizing the circuit efficiency as well as minimizing the systolic delay, and differential neural architecture search (NAS) method for the high accuracy multi-bit-width network generation. The proposed accelerator has been practically deployed on Xilinx ZCU102 with accelerating NAS optimized VGG16 and Resnet18 networks as case studies. Average performance on accelerating the convolutional layer in VGG16 and Resnet18 is 1289GOPs and 1155GOPs, respectively. Throughput for running the full multi-bit-width VGG16 network is 870.73 GOPS at 250MHz, which has exceeded all of previous CNN accelerators on the same platform.

关键词： systolic array fpga CNN accelerator multi-bit-width CNN

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A Fractal Astronomical Correlator Based on fpga Cluster with Scalability 23

A Fractal Astronomical Correlator Based on FPGA Cluster with...

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Proceedings of the 2023 acm/sigda international symposium on field programmable gate arrays

作者： Lin Shu Long Xiao Yafang Song Qiuxiang Fan Guitian Fang Jie Hao Institute of Automation Chinese Academy of Sciences & Guangdong Institute of Artificial Intelligence and Advanced Computing Beijing China Institute of Automation Chinese Academy of Sciences Beijing China Guangdong Institute of Artificial Intelligence and Advanced Computing Guangzhou China

ISBN: (纸本)9781450394178

Correlation is a highly computationally intensive and data-intensive signal processing application that is used heavily in radio astronomy for imaging and other measurements. For example, the next generation radio telescope, Square Kilometer Array Low (SKA-L), needs a correlator that calculates up to 22 million cross products, which is a real-time system with continuous input data rates of 6 terabits per second and equivalent computation of 2 Peta-operations per second. Therefore, a flexible and scalable solution with high performance per watt is very urgent and meaningful. In this work, a flexible FX correlation architecture based on fpga cluster is proposed, which can be fractal in subsystem level, engine level and calculation module level, simplifying the complexity of data distribution network to increase the system's scalability. The interconnect network between processing engines is a new two-stage solution, using self-developed data redistribution hardware to decouple full bandwidth correlation into several independent sub-bands' computation. And the most intensive calculations, cross-multiplications among all the antennas, are modularly designed under MATLAB Simulink and AMD Xilinx System Generator, which are parametrized to scale to arbitrary antenna numbers with optional parallel granularity to minimize development effort on different fpga or for different applications. What's more, a fully fpga-based FX correlator for a large array with 202 antennas, consisting of 26 F Engines based on AMD Xilinx Kintex-7 325T fpgas, 13 X Engines based on AMD Xilinx Kintex ultrascale KU115 fpgas, has been deployed in 2022, which is the largest full fpga-based astronomical correlator as we know.

关键词： fpga cluster scalability fractal computing correlation modular design

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Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on fpga Platform 22

Ultra Low-Complexity Implementation of Binary Ring-LWE based...

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Proceedings of the 2022 acm/sigda international symposium on field-programmable gate arrays

作者： Jiafeng Xie Pengzhou He Tianyou Bao Villanova University Villanova PA USA

ISBN: (纸本)9781450391498

Post-quantum cryptography (PQC) has drawn substantial attention from various communities recently since the existing public-key cryptosystems are proven to be vulnerable to the attacks launched from well-established quantum computers. The Ring-Learning-with-Errors (Ring-LWE)-based encryption scheme is an important lattice-based PQC. The binary Ring-LWE (BRLWE), a variant of Ring-LWE, has been proposed to build lightweight PQC with much smaller complexity for resource-constrained applications. So far, however, limited reports have been released on the ultra low-complexity implementations of the BRLWE-based scheme (especially on the hardware platform). Therefore, in this paper, we propose to obtain a novel implementation of the BRLWE-based PQC on the field-programmable gate Array (fpga) platform with ultra low-complexity. We have proposed three layers of coherent interdependent efforts: (i) motivation and the related derivation for the key operation of the BRLWE-based scheme are presented first; (ii) the corresponding hardware structure is then efficiently mapped from the proposed algorithm with the help of algorithm-architecture co-implementation techniques; (iii) the final complexity analysis and fpga implementation results show that the proposed designs have significantly smaller area-time complexities than the state-of-the-art designs. Overall, the proposed designs possess multiple unique features and thus are desirable for emerging lightweight applications.

关键词： pqc ultra low-complexity brlwe-based encryption scheme fpga

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AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both fpgas and ASICs 20

AutoDNNchip: An Automated DNN Chip Predictor and Builder for...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Xu, Pengfei Zhang, Xiaofan Hao, Cong Zhao, Yang Zhang, Yongan Wang, Yue Li, Chaojian Guan, Zetong Chen, Deming Lin, Yingyan Rice Univ Houston TX 77251 USA Univ Illinois Champaign IL USA

ISBN: (纸本)9781450370998

Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for domain-specific hardware accelerators (i.e., DNN chips). However, designing DNN chips is non-trivial because: (1) mainstream DNNs have millions of parameters and operations;(2) the design space is large due to the numerous design choices of dataflows, processing elements, memory hierarchy, etc.;and (3) an algorithm/hardware co-design is needed to allow the same DNN functionality to have a different decomposition that would require different hardware IPs that correspond to dramatically different performance/energy/area tradeoffs. Therefore, DNN chips often take months to years to design and require a large team of cross-disciplinary experts. To enable fast and effective DNN chip design, we propose AutoDNNchip - a DNN chip generator that can automatically generate both fpga- and ASIC-based DNN chip implementation (i.e., synthesizable RTL code with optimized algorithm-to-hardware mapping (i.e., dataflow)) given DNNs from machine learning frameworks (e.g., PyTorch) for a designated application and dataset without humans in the loop. Specifically, AutoDNNchip consists of two integrated enablers: (1) a Chip Predictor, built on top of a graph-based accelerator representation, which can accurately and efficiently predict a DNN accelerator's energy, throughput, latency, and area based on the DNN model parameters, hardware configuration, technology-based IPs, and platform constraints;and (2) a Chip Builder, which can automatically explore the design space of DNN chips (including IP selection, block configuration, resource balance, etc.), optimize chip design via the Chip Predictor, and then generate synthesizable RTL code with optimized dataflows to achieve the target design metrics. Experimental results show that our Chip Predictor's predicted performance differs from the real-measured one by <10% when validated using 15 DNN models and 4 platforms (edge-fpga/TPU/GPU and ASIC). Furthermore, b

关键词： dnn accelerator generator automated dnn accelerator design fpga dnn accelerator performance prediction asic

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LUXOR: An fpga Logic Cell Architecture for Efficient Compressor Tree Implementations 20

LUXOR: An FPGA Logic Cell Architecture for Efficient Compres...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Rasoulinezhad, Seyedramin Siddharta Zhou, Hao Wang, Lingli Boland, David Leong, Philip H. W. Univ Sydney Sch Elect & Informat Engn Sydney NSW 2006 Australia Fudan Univ State Key Lab ASIC & Syst Shanghai 201203 Peoples R China

ISBN: (纸本)9781450370998

We propose two tiers of modiications to fpga logic cell architecture to deliver a variety of performance and utilization beneits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-speciic modiications to both Xilinx and Intel fpgas, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modiications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13-19% in logic utilization on micro-benchmarks from a variety of *** benchmarks beneit the most with an average reduction of 37-47% in logic utilization, which is due to the highly-eicient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells.

关键词： logic elements fpga architectures compressor trees

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An Integrity Checking Framework for AXI Protocol in Multi-tenant fpga 22

An Integrity Checking Framework for AXI Protocol in Multi-te...

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Proceedings of the 2022 acm/sigda international symposium on field-programmable gate arrays

作者： Yukui Luo Yuheng Zhang Shijin Duan Xiaolin Xu Northeastern University Boston MA USA

ISBN: (纸本)9781450391498

fpgas have been widely deployed in cloud servers a promising computing infrastructure. It is envisioned that through the fpga virtualization, multiple users will be able to share the hardware resources of an fpga chip. Although bringing great benefits like highly efficient resource utilization, such multi-tenant cloud-fpga also raises security concerns. While most existing works have demonstrated that an application running on a multi-tenant fpga is vulnerable to fault injection attacks introduced by the power distribution network (PDN) disturbance on an fpga, few of them consider the impact of such power attacks on the data interface of an fpga. As a critical component in charge of the data transmission between intra-fpga IPs and/or inter-fpga components, the runtime integrity of the communication interface plays an essential role in the security of a multi-tenant fpga. This work, we investigate the impact of the PDN-based fault injection attacks on the Advanced eXtensible Interface (AXI) protocol as a case study. We find that like other circuit applications, the embedded AXI protocol interface also suffers from the PDN-based fault injection attacks, but with unique fault characteristics. To mitigate such vulnerabilities of the AXI in multi-tenant cloud-fpga, we propose a runtime integrity checking framework. We evaluate the proposed framework with practical data transmission setup to demonstrate the effectiveness of the proposed scheme.

关键词： multi-tenant fpga integrity checking

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