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Establishing Trust in Microelectronics 20

Establishing Trust in Microelectronics

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Lerner, Lee W. Georgia Inst Technol Georgia Tech Res Inst Atlanta GA 30332 USA

ISBN: (纸本)9781450370998

In recent years, substantial attention has been drawn to vulnerabilities in the architectural design of microelectronics, as well as the security of their global supply chains. In reality, establishing trust in microelectronics requires broader considerations, from verification of the software leveraged to implement hardware designs, to analyzing third-party intellectual property cores, all the way to run-time design assurance and periodic device screening post-deployment. These concerns are relevant to stakeholders at all levels, from small independent design houses all the way to multi-national strategic interests. One notable example of the latter is the U.S. Department of Defense's Trusted and Assured Microelectronics (T&AM) program, which seeks assured access to state-of-the-art foundries through modern trust and assurance methods and demonstrations [1]. This talk will describe research efforts at the Georgia Tech Research Institute centered around providing assurance of fpgas. Current research thrusts include the development of verification techniques at multiple stages of the design process, including vendor design software execution, implementation of user designs, and even the operation of the underlying physical device hardware itself. For example, to address trust in synthesis and implementation of high-level user source code, we discuss the development of canary circuits which are compiled alongside user design circuits and can be independently inspected and verified to ensure adherence to user-defined implementation rules. Additionally, we discuss one avenue for providing trust in vendor hardware devices through our development of Independent Functional Test (IFT) suites.

关键词： Microelectronics fpga Security Cybersecurity Trustworthy Computing Trust Assurance Verification

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DecGNN: A Framework for Mapping Decoupled GNN Models onto CPU-fpga Heterogeneous Platform 22

DecGNN: A Framework for Mapping Decoupled GNN Models onto CP...

引用

Proceedings of the 2022 acm/sigda international symposium on field-programmable gate arrays

作者： Bingyi Zhang Hanqing Zeng Viktor K. Prasanna University of Southern California Los Angeles CA USA

ISBN: (纸本)9781450391498

A well-known issue in mini-batch GNN inference is neighborhood explosion. This results in two challenges for its hardware acceleration: (1) high computation and communication costs resulting in high latency, and (2) low computation-to-communication ratio leading to low hardware utilization. To address these challenges, we propose a hardware mapping framework following the recently proposed GNN design principle of model depth-receptive field decoupling. We show that Decoupled GNNs enjoy significantly higher computation-to-communication ratio, therefore, are more suitable for hardware acceleration. To efficiently map Decoupled GNNs onto CPU-fpga heterogeneous platforms, we propose the following model-architecture co-optimizations: (1) Model instantiation: according to the bandwidth and computation resources, we determine the number of GNN layers to achieve high hardware utilization; (2) Neighbor selection: to meet the application constraint, we select a small number of important neighbors surrounding the target vertices to improve the throughput without sacrificing accuracy; (3) Hardware mapping: given the model and neighborhood defined above, we determine the accelerator parameters based on our novel hardware templates, enabling fast computation of GNN inference workloads. We evaluate our framework on two state-of-the-art fpga platforms, using two models (GCN, GraphSAGE). Experiments show that the resulting designs achieve high hardware utilization 88%-94% and significant speedup (1.1x-2.5x) compared with the implementations on state-of-the-art CPU-GPU platform.

关键词： roofline model graph neural network cpu-fpga heterogeneous platform

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Efficient fpga-based ECDSA Verification Engine For Permissioned Blockchains 22

Efficient FPGA-based ECDSA Verification Engine For Permissio...

引用

Proceedings of the 2022 acm/sigda international symposium on field-programmable gate arrays

作者： Rashmi Agrawal Ji Yang Haris Javaid Boston University Boston MA USA Xilinx San Jose CA USA Xilinx Singapore Singapore

ISBN: (纸本)9781450391498

Permissioned blockchain platforms heavily depend on cryptography to provide a layer of trust within the blockchain network, thus verification of cryptographic signatures often becomes the bottleneck. ECDSA is the most commonly used cryptographic scheme in permissioned blockchains. In this work, we propose an efficient implementation of ECDSA signature verification on fpga, in order to improve performance of permissioned blockchains that aim to use fpga-based hardware accelerators. We propose several optimizations for modular arithmetic (e.g., custom multipliers and fast modular reduction) and point arithmetic (e.g., reduced number of point double and addition operations, and optimal width NAF representation). Based on these optimized modular and point arithmetic modules, we propose an ECDSA verification engine that can be used by any application for fast verification of signatures. We further optimize our ECDSA verification engine for Hyperledger Fabric (one of the most widely used blockchain platforms) by moving carefully selected operations to a precomputation block, thus simplifying the critical path of ECDSA signature verification. Our ECDSA engine running at 250MHz on Xilinx Alveo U250 accelerator card can perform a verification in 760 microseconds with a throughput of 1,315 verifications/second, which is ~2.5 times faster than state-of-the-art fpga-based implementations. Our Hyperledger Fabric-specific ECDSA engine can perform a verification in 368 microseconds, and 2,717 verifications/second. With 10 engines, Hyperledger Fabric can achieve a throughput of 7,520 transactions/second.

关键词： ecdsa signature verification fpga hyperledger fabric

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Synthesized Garbage Collection for fpga Accelerators 22

Synthesized Garbage Collection for FPGA Accelerators

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Proceedings of the 2022 acm/sigda international symposium on field-programmable gate arrays

作者： Martha Barker Stephen A. Edwards Martha A. Kim Columbia University New York NY USA

ISBN: (纸本)9781450391498

Speed and ease of accelerator design is a growing need. High level programming languages have provided significant gains in the software world, but lag in the hardware realm. We present a hardware implementation of a garbage collector, which automates memory management, one of the major conveniences of modern software languages. Our garbage collector is integrated with a Haskell to hardware HLS flow. The collector runs concurrently with the application, using already-idle memory slots to do its work with little to no impact on performance. To achieve this, our collector exploits rapid synchronization that is straightforward in hardware but very difficult in software. With this synchronization, the collector is able to safely pop in and out of very fine pockets of idleness on a cycle by cycle, heap by heap basis. In most cases our collector incurred negligible overhead, and slowed the application only when the heaps were so tiny that the application was unable to proceed with its operation until the collector had freed more space. Our experiments further show that our concurrent collector performs best under an eager collection policy that collects garbage well-before the application exhausts the available memory. Although this eager strategy performs more collection operations than strictly necessary, the application never pauses and the collector operates entirely in the background.

关键词： garbage collection hls

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A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on fpga 22

A High Throughput Multi-bit-width 3D Systolic Accelerator fo...

引用

Proceedings of the 2022 acm/sigda international symposium on field-programmable gate arrays

作者： Mingqiang Huang Yucen Liu Quan Cheng Shuxin Yang Kai Li Junyi Luo Zhengke Yang Qiufeng Li Hao Yu Changhai Man Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China Southern University of Science and Technology Shenzhen China

ISBN: (纸本)9781450391498

Neural architecture search (NAS) optimized multi-bit-width convolutional neural network (CNN) maintains the balance between network performance and efficiency, thus enlightening a promising method for accurate yet energy-efficient edge computing. In this work, we propose a high throughput three-dimensional (3D) systolic accelerator for NAS optimized CNNs, in which the input feature matrix, weight matrix and output feature matrix are delivering vertically, horizontally and perpendicularly through the systolic array respectively. With 3D systolic data flow, the processing time and logic resources consumption can be both reduced compared to the classical non-stationary systolic array. Besides, Booth-based multi-bit-width (INT2/4/8) multiply-add-accumulation (MAC) unit is developed within the 3D systolic accelerator. Deployed on fpga platform Xilinx ZCU102, peek performance of the convolutional layer can reach as high as 2775 GOPS for INT2, 1650 GOPS for INT4, and 816 GOPS for INT8 respectively. The average performance on accelerating full NAS VGG16 network is 647 GOPS.

关键词： nas multi-bit-width cnn systolic array

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Xilinx Adaptive Compute Acceleration Platform: Versal™ Architecture

Xilinx Adaptive Compute Acceleration Platform: Versal™ Arch...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Gaide, Brian Gaitonde, Dinesh Ravishankar, Chirag Bauer, Trevor Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450361378

In this paper we describe Xilinx's Versal (TM) Adaptive Compute Acceleration Platform (ACAP). ACAP is a hybrid compute platform that tightly integrates traditional fpga programmable fabric, software programmable processors and software programmable accelerator engines. ACAP improves over the programmability of traditional reconfigurable platforms by introducing newer compute models in the form of software programmable accelerators and by separating out the data movement architecture from the compute architecture. The Versal architecture includes a host of new capabilities, including a chip-pervasive programmable Network-on-Chip (NoC), Imux Registers, compute shell, more advanced SSIT, adaptive deskew of global clocks, faster configuration, and other new programmable elements as well as enhancements to the CLB and interconnect. We discuss these architectural developments and highlight their key motivations and differences in relation to traditional fpga architectures.

关键词： ACAP Versal fpga Stacked Silicon SSIT Adaptable Compute Acceleration Platform Math Engine NoC fpga Architecture fpga CAD Xilinx

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Build Your Own Domain-specific Solutions with RapidWright Invited Tutorial 19

Build Your Own Domain-specific Solutions with RapidWright In...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Lavin, Chris Kaviani, Alireza Xilinx Res Labs San Jose CA 95124 USA

ISBN: (纸本)9781450361378

As the complexity of programmable architectures increases with advances in silicon process technology, there is a growing need to extract greater productivity and performance from the tools. Due to their inherent reconfigurability, fpgas are proving to be valuable targets for more efficient domain-specific architectures. However, fpga implementation tools are designed for a broad set of applications. In this paper we describe RapidWright, an open source framework that enables customized implementations for Xilinx fpgas. RapidWright enables implementation tools that can take advantage of the great potential of domain-specific attributes-leading to greater productivity and performance. The focus of this paper is to provide an introductory reference of RapidWright and its use cases so that others may be empowered to adapt their implementations to their domain-specific applications.

关键词： Domain-specific Open Source fpga Xilinx Vivado

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AFFIX: Automatic Acceleration Framework for fpga Implementation of OpenVX Vision Algorithms 19

AFFIX: Automatic Acceleration Framework for FPGA Implementat...

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Taheri, Sajjad Behnam, Payman Bozorgzadeh, Eli Veidenbaum, Alexander Nicolau, Alexandru Univ Calif Irvine Irvine CA 92697 USA Univ Utah Salt Lake City UT USA

ISBN: (纸本)9781450361378

Computer vision algorithms are computationally expensive and difficult to implement efficiently. field programmable gate arrays (fpga)s offer a promising direction to reduce the computation cost by exploiting hardware parallelism. However, it is difficult to translate vision algorithms to fpga bitstream efficiently. OpenVX is an industry standard for graph-based representation of vision algorithms. It defines a set of widely used vision kernels and data structures that can be used to form a Directed Acyclic Graph (DAG) to represent a vision algorithm. This paper proposes a framework for automatic fpga acceleration of computer vision algorithms based on OpenVX specification, called AFFIX. AFFIX receives a vision algorithm formed using the OpenVX and generates a heterogeneous CPU-fpga implementation. AFFIX incorporates several high level and low-level optimization methods to improve the efficiency of the fpga implementation. It provides a configurable and extensible framework that enables vision algorithm developers to quickly develop, verify and test fpga implementations of vision algorithms. We demonstrate the effectiveness of the proposed framework via development and evaluations of multiple vision algorithms.

关键词： Acceleration Computer vision fpga OpenVX OpenCL

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The Network Management Unit (NMU): Securing Network Access for Direct-Connected fpgas 19

The Network Management Unit (NMU): Securing Network Access f...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Rozhko, Daniel Chow, Paul Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450361378

Reconfigurable compute devices, namely field programmable gate arrays (fpga), have increasingly been deployed in datacenters and cloud infrastructures. Such devices have proven effective at performing certain types of compute tasks, often performing these tasks faster, with lower latency, at a higher throughput, and/or at lower power than traditional compute devices (e.g. CPUs). Some recent works have demonstrated the benefits of deploying such devices as direct-connected nodes, i.e., the fpgas are connected directly to the datacenters' network infrastructure. In this work, we introduce the concept of the Network Management Unit (NMU), which secures the network from potentially unwarranted access from malicious or malfunctioning fpga applications;specifically, the NMU targets network traffic originating from (or targeted towards) an application resident solely on the fpga itself. We argue that this is a necessary feature of direct-connected reconfigurable compute devices. We present the design of several NMUs, introduce a taxonomy for describing these different designs, and analyze the trade-offs of each design. The NMUs discussed range from those that employ hairpin routing techniques to push management to the next level switch, to those that perform routing and access control directly.

关键词： fpga Reconfigurable Computing Networking Management Access Control Routing Encapsulation

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Reconfigurable Convolutional Kernels for Neural Networks on fpgas 19

Reconfigurable Convolutional Kernels for Neural Networks on ...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Hardieck, Martin Kumm, Martin Moeller, Konrad Zipf, Peter Univ Kassel Kassel Germany

ISBN: (纸本)9781450361378

Convolutional neural networks (CNNs) gained great success in machine learning applications and much attention was paid to their acceleration on field programmable gate arrays (fpgas). The most demanding computational complexity of CNNs is found in the convolutional layers, which account for 90% of the total operations. The fact that parameters in convolutional layers do not change over a long time interval in weight stationary CNNs allows the use of reconfiguration to reduce the resource requirements. This work proposes several alternative reconfiguration schemes that significantly reduce the complexity of sum-of-products operations. The proposed direct configuration schemes provide the least resource requirements and fast reconfiguration times of 32 clock cycles but require additional memory for the pre-computed configurations. The proposed online reconfiguration scheme uses an online computation of the LUT contents to avoid this memory overhead. Finally, a scheme that duplicates the reconfigurable LUTs is proposed for which the reconfiguration time can be completely hidden in the computation time. Combined with a few online reconfiguration circuits, this provides the same configuration memory and configuration time as a conventional parallel kernel but offers large resource reductions of up to 80% of the LUTs.

关键词： Convolutional Neural Networks fpga runtime reconfiguration

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