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Temporal Thermal Covert Channels in Cloud fpgas 19

Temporal Thermal Covert Channels in Cloud FPGAs

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Tian, Shanquan Szefer, Jakub Yale Univ New Haven CT 06520 USA

ISBN: (纸本)9781450361378

With increasing interest in Cloud fpgas, such as Amazon's EC2 F1 instances or Microsoft's Azure with Catapult servers, fpgas in cloud computing infrastructures can become targets for information leakages via convert channel communication. Cloud fpgas leverage temporal sharing of the fpga resources between users. This paper shows that heat generated by one user can be observed by another user who later uses the same fpga. The covert data transfer can be achieved through simple on-off keying (OOK) and use of multiple fpga boards in parallel significantly improves data throughput. The new temporal thermal covert channel is demonstrated on Microsoft's Catapult servers with fpgas running remotely in the Texas Advanced Computing Center (TACC). A number of defenses against the new temporal thermal covert channel are presented at the end of the paper.

关键词： Covert Channels Cloud fpga Ring Oscillator fpga Security

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Fractal Synthesis - Invited Tutorial 19

Fractal Synthesis - Invited Tutorial

引用

acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Langhammer, Martin Baeckler, Gregg Gribok, Sergey Intel PSG Bayan Lepas Malaysia

ISBN: (纸本)9781450361378

This paper will describe Fractal Synthesis, which is a new set of synthesis, clustering, and packing algorithms for fpga devices, which dramatically increases the utilization and effective performance for arithmetic rich designs. The emergence of AI inferencing as a significant new fpga application has brought some of the shortcomings of the fpga and current design flows into focus. We describe new results where near 100% logic utilization of the fpga is not only possible, but deterministic, with consistent high clock rates. Alternately, smaller datapaths can be synthesized, and combined to make chip filling designs. In one benchmark consisting of purely arithmetic datapath for a large Stratix (R) 10 fpga (E-2 speedgrade), we will show 92% logic utilization at 460 MHz for an automatically placed arithmetic datapath, and 410MHz with 97% logic utilization. Furthermore, we describe new results, where these performance and density level can be applied to non-arithmetic designs, by extending these techniques to placement.

关键词： fpga Fractal Synthesis Fractal Packing

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Network-on-Chip programmable Platform in Versal™ ACAP Architecture

Network-on-Chip Programmable Platform in Versal™ ACAP Archi...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Swarbrick, Ian Gaitonde, Dinesh Ahmad, Sagheer Gaide, Brian Arbel, Ygal Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450361378

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal (TM) architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in fpga devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, fpga fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

关键词： ACAP Versal fpga Stacked Silicon SSIT Adaptable Compute Acceleration Platform NoC fpga Architecture fpga CAD Xilinx

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Stealing Neural Network Structure through Remote fpga Side-channel Analysis 21

Stealing Neural Network Structure through Remote FPGA Side-c...

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Yicheng Zhang Rozhin Yasaei Hao Chen Zhou Li Mohammad Abdullah Al Faruque University of California Irvine Irvine CA USA

ISBN: (纸本)9781450382182

Deep Neural Network (DNN) models have been extensively developed by companies for a wide range of applications. The development of a customized DNN model with great performance requires costly investments, and its structure (layers and hyper-parameters) is considered intellectual property and holds immense value. However, in this paper, we found the model secret is vulnerable when a cloud-based fpga accelerator executes it. We demonstrate an end-to-end attack based on remote power side-channel analysis and machine-learning-based secret inference against different DNN models. The evaluation result shows that an attacker can reconstruct the layer and hyper-parameter sequence at over 90% accuracy using our method, which can significantly reduce her model development workload. We believe the threat presented by our attack is tangible, and new defense mechanisms should be developed against this threat.

关键词： fpga deep-learning model side-channel attack

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Extending High-Level Synthesis for Task-Parallel Programs 21

Extending High-Level Synthesis for Task-Parallel Programs

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Yuze Chi Licheng Guo Young-kyu Choi Jie Wang Jason Cong University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450382182

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (fpga) accelerators in many application domains in recent years, thanks to its competitive quality of result (QoR) and short development cycle compared with the traditional register-transfer level (RTL) design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools support task-parallel programs, the productivity is greatly limited in the code development, correctness verification, and QoR tuning cycles, due to the poor programmability, restricted software simulation, and slow code generation, respectively. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel fpga *** this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, universal software simulation, and fast code generation to overcome these limitations. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. The correctness verification and the iterative QoR tuning cycles are both greatly accelerated by 3.2× and 6.8×, respectively.

关键词： high-level synthesis task-parallel program field-programmable gate array

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Characterization of Long Wire Data Leakage in Deep Submicron fpgas 19

Characterization of Long Wire Data Leakage in Deep Submicron...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Provelengios, George Ramesh, Chethan Patil, Shivukumar B. Eguro, Ken Tessier, Russell Holcomb, Daniel UMass Amherst Amherst MA 01003 USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781450361378

The simultaneous use of fpgas by multiple tenants has recently been shown to potentially expose sensitive information without the victim's knowledge. For example, neighboring long wires in SRAM-based fpgas have been shown to allow for clandestine data exfiltration. In this work, we explore distinct characteristics of this signal crosstalk that could be used to enhance or prevent information leakage. First, we develop a mechanism to characterize the crosstalk coupling that exists between neighboring wires at the femtosecond scale. Second, we show that it is possible to reverse engineer channel layouts by determining which pairs of routing resources/links in the channel exhibit coupling to each other even if this information is not provided by the fpga vendor. To fully characterize these effects, we examine long wire coupling on different types of wires across three devices implemented in different technology nodes from 65 to 20 nm. We experimentally demonstrate that information leakage is apparent for all three fpga families.

关键词： fpga side channel crosstalk

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Compute-Efficient Neural-Network Acceleration 19

Compute-Efficient Neural-Network Acceleration

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Wu, Ephrem Zhang, Xiaoqian Berman, David Cho, Inkeun Thendean, John Xilinx Inc Silicon Architecture San Jose CA 95124 USA

ISBN: (纸本)9781450361378

To enhance the performance of fpga-based neural-network accelerators, maximizing both operating clock rates and compute efficiency is paramount. Streamlining data movement between memory and compute holds the key to boosting these metrics. To unleash latent performance in fpga-based inference processors, we outline a convolutional neural network accelerator that operates at 92.9% of the peak fpga clock rate. First, we map neural-network operators to a minimalist hardware architecture to simplify data movement between memory and compute. Doing so enables the design to close timing at high clock rates. Second, we describe a schedule that keeps compute utilization high. We apply this architecture to classify MNIST, CIFAR-10, and ImageNet datasets. This design achieves 95.5% compute efficiency with GoogLeNet, whose nested topology makes creating an efficient design especially challenging.

关键词： Convolutional neural networks compute efficiency fpga GoogLeNet image classification reduced precision tensor processing accelerator deep learning reconfigurable architecture

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Rapid Cycle-Accurate Simulator for High-Level Synthesis 19

Rapid Cycle-Accurate Simulator for High-Level Synthesis

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chi, Yuze Choi, Young-kyu Cong, Jason Wang, Jie Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781450361378

A large semantic gap between the high-level synthesis (HLS) design and the low-level (on-board or RTL) simulation environment often creates a barrier for those who are not fpga experts. Moreover, such low-level simulation takes a long time to complete. Software-based HLS simulators can help bridge this gap and accelerate the simulation process;however, we found that the current fpga HLS commercial software simulators sometimes produce incorrect results. In order to solve this correctness issue while maintaining the high speed of a software-based simulator, this paper proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract the scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. Experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation.

关键词： high-level synthesis simulation acceleration source-to-source transformation fpga

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FASED: fpga-Accelerated Simulation and Evaluation of DRAM 19

FASED: FPGA-Accelerated Simulation and Evaluation of DRAM

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Biancolin, David Karandikar, Sagar Kim, Donggyu Koenig, Jack Waterman, Andrew Bachrach, Jonathan Asanovic, Krste Univ Calif Berkeley Dept Elect Engn & Comp Sci ADEPT Lab Berkeley CA 94720 USA SiFive Inc San Mateo CA USA

ISBN: (纸本)9781450361378

Recent work in fpga-accelerated simulation of ASICs has shown that much of a simulator can be automatically generated from ASIC RTL. Alas, these works rely on simple models of the outer cache hierarchy and DRAM, as mapping ASIC RTL for these components into an fpga fabric is too complex and resource intensive. To improve fpga simulation model accuracy, we present fased, a parameterized generator of composable, high-fidelity, fpga-hosted last-level-cache and DRAM models. fased instances are highly performant, yet they maintain timing faithfulness independently of the behavior of the host-fpga memory system. For a given scheduling policy, a single fased instance can model nearly the entire space of realizable single-channel DDR3 memory organizations, without resynthesizing the simulator RTL. We demonstrate fased by integrating it into a flow that automatically transforms RTL for multicore RISC-V processors into full-system simulators that execute at up to 150 target MHz on cloud-hosted fpgas.

关键词： emulation fpga prototyping memory systems

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LANMC: LSTM-Assisted Non-Rigid Motion Correction on fpga for Calcium Image Stabilization 19

LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chen, Zhe Blair, Hugh T. Cong, Jason Univ Calif Los Angeles Los Angeles CA 90095 USA

ISBN: (纸本)9781450361378

Calcium imaging is an emerging technique for visualizing and recording neural population activity at large scale in vivo. Non-rigid motion correction is a critical step in the calcium image analysis pipeline due to non-uniform deformations of the brain tissue during the data collection. Existing non-rigid motion correction algorithms are costly in computation time and energy, and it is hard to implement such algorithm in real time on an embedded device. In this paper, we propose LANMC, an LSTM-assisted non-rigid motion correction method for real-time calcium image stabilization. This method reduces the computational cost by using the LSTM inference to predict the non-rigid motion. Based on this method, we demonstrate a non-rigid motion correction implementation for real-time calcium image stabilization on fpga. Experimental results show that the non-rigid motion correction can be accomplished within 80 mu s on the Ultra96 under 300 MHz frequency, and the latency outperforms that on a 12-thread CPU by 82x.

关键词： Calcium image long short-term memory (LSTM) motion correction

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