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RIFL: A Reliable Link Layer Network Protocol for fpga-to-fpga Communication 21

RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPG...

引用

The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Qianfeng (Clark) Shen Jun Zheng Paul Chow University of Toronto Toronto ON Canada Alibaba Group Sunnyvale CA USA

ISBN: (纸本)9781450382182

More and more latency-sensitive applications are being introduced into the data center. Performance of such applications can be limited by the high latency of the network interconnect. Because the conventional network stack is designed not only for LAN, but also for WAN, it carries a great amount of redundancy that is not required in a data center network. This paper introduces the concept of a three-layer protocol stack that can replace the conventional network stack and fulfill the exact demands of data center network communications. The detailed design and implementation of the first layer of the stack, which we call RIFL, is presented. A novel low latency in-band hop-by-hop re-transmission protocol is proposed and adopted in RIFL, which guarantees lossless transmission for links whose longest wire segment is no more than 150 meters. Experimental results show that RIFL achieves 218 nanoseconds round-trip latency on 3 meter zero-hop links, at a throughput of 104.7 Gbps. RIFL is a multi-lane protocol with scalable throughput from 500 Mbps to above 200 Gbps. It is portable to most of the recent fpgas. It can be the enabler of low latency, high throughput, flexible, scalable, and lossless data center networks.

关键词： low latency lossless link layer data center network

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A Framework for Optimizing GCN Inference on fpga 21

A Framework for Optimizing GCN Inference on FPGA

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Bingyi Zhang Rajgopal Kannan Viktor Prasanna University of Southern California Los Angeles CA USA US Army Research Lab Los Angeles CA USA

ISBN: (纸本)9781450382182

Graph convolutional networks (GCNs) have revolutionized many big data applications. However, accelerating GCN inference is still challenging due to (1) massive external memory traffic and irregular memory access, (2) workload imbalance because of the skewed degree distribution, and (3) intra-stage load imbalance between feature aggregation and feature transformation steps. To address the above challenges, we propose a framework to optimize GCN inference on fpga. First, we propose a novel Partition-Centric Feature Aggregation (PCFA) scheme to increase the data locality and reduce the number of random memory accesses in feature aggregation step. Second, we propose a novel hardware architecture to enable pipelined execution of the two heterogeneous computation steps. Then, a low-overhead task scheduling strategy is proposed to achieve stall-free execution of the two computation steps. Third, we provide a complete GCN acceleration framework on fpga, and define key parameters for users to fine-tune the throughput. The model-specific operators can be customized to support a wide-range of GCN models. Using our framework, we design accelerators on a state-of-the-art fpga. We evaluate our work using widely used datasets and. Experimental results show the accelerators produced by our framework achieve significant speedup compared with state-of-the-art implementations on CPU (≈100x), GPU (≈30x), and fpga (4.5-32x).

关键词： fpga framework graph neural network hardware acceleration

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Efficient and Effective Sparse LSTM on fpga with Bank-Balanced Sparsity 19

Efficient and Effective Sparse LSTM on FPGA with Bank-Balanc...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Cao, Shijie Zhang, Chen Yao, Zhuliang Xiao, Wencong Nie, Lanshun Zhan, Dechen Liu, Yunxin Wu, Ming Zhang, Lintao Harbin Inst Technol Harbin Peoples R China Microsoft Res Redmond WA USA Tsinghua Univ Beijing Peoples R China Beihang Univ Beijing Peoples R China

ISBN: (纸本)9781450361378

Neural networks based on Long Short-Term Memory (LSTM) are widely deployed in latency-sensitive language and speech applications. To speed up LSTM inference, previous research proposes weight pruning techniques to reduce computational cost. Unfortunately, irregular computation and memory accesses in unrestricted sparse LSTM limit the realizable parallelism, especially when implemented on fpga. To address this issue, some researchers propose block-based sparsity patterns to increase the regularity of sparse weight matrices, but these approaches suffer from deteriorated prediction accuracy. This work presents Bank-Balanced Sparsity (BBS), a novel sparsity pattern that can maintain model accuracy at a high sparsity level while still enable an efficient fpga implementation. BBS partitions each weight matrix row into banks for parallel computing, while adopts fine-grained pruning inside each bank to maintain model accuracy. We develop a 3-step software-hardware co-optimization approach to apply BBS in real fpga hardware. First, we propose a bank-balanced pruning method to induce the BBS pattern on weight matrices. Then we introduce a decoding-free sparse matrix format, Compressed Sparse Banks (CSB), that transparently exposes inter-bank parallelism in BBS to hardware. Finally, we design an fpga accelerator that takes advantage of BBS to eliminate irregular computation and memory accesses. Implemented on Intel Arria-10 fpga, the BBS accelerator can achieve 750.9 GOPs on sparse LSTM networks with a batch size of 1. Compared to stateof-the-art fpga accelerators for LSTM with different compression techniques, the BBS accelerator achieves 2.3 similar to 3.7x improvement on energy efficiency and 7.0 similar to 34.4x reduction on latency with negligible loss of model accuracy.

关键词： fpga Deep Neural Networks LSTM Weight Pruning Inference Bank-Balanced Sparsity

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Improving Performance of Graph Processing on fpga-DRAM Platform by Two-level Vertex Caching 19

Improving Performance of Graph Processing on FPGA-DRAM Platf...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Shao, Zhiyuan Li, Ruoshi Hu, Diqing Liao, Xiaofei Jin, Hai Huazhong Univ Sci & Technol Sch Comp Sci & Technol Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol Sch Comp Sci & Technol Informat Storage & Opt Display Div Wuhan 430074 Peoples R China

ISBN: (纸本)9781450361378

In recent years, graph processing attracts lots of attention due to its broad applicability in solving real-world problems. With the flexibility and programmability, fpga platforms provide the opportunity of processing the graph data with high efficiency. On fpga-DRAM platforms, the state-of-art solution of graph processing (i.e., Fore-Graph) attaches each pipeline with local vertex buffers to cache the source and destination vertices during processing. Such one-level vertex caching mechanism, however, results in excessive amounts of vertex data transmissions that consume the precious DRAM bandwidth, and frequent pipeline stalls that waste the processing power of the fpga. In this paper, we propose a two-level vertex caching mechanism to improve the performance of graph processing on fpga-DRAM platforms by reducing the amounts of vertex data transmissions and pipeline stalls during the execution of graph algorithms. We build a system, named as FabGraph, to implement such two-level vertex caching mechanism by using available on-chip storage resources, including BRAM and UltraRAM. Experimental results show that: FabGraph achieves up to 3.1x and 2.5x speedups over ForeGraph for BFS and PageRank respectively, on the fpga board with relatively large BRAM;and up to 3.1x and 3.0x speedups over ForeGraph for BFS and PageRank respectively, on the fpga board with small BRAM but large UltraRAM. Our experience in this paper suggests that the two-level vertex caching design is effective in improving the performance of graph processing on fpga-DRAM platforms.

关键词： Hardware Accelerators Graph Analytics

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3M-AI: A Multi-task and Multi-core Virtualization Framework for Multi-fpga AI Systems in the Cloud 21

3M-AI: A Multi-task and Multi-core Virtualization Framework ...

引用

The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Shulin Zeng Guohao Dai Hanbo Sun Jun Liu Hongren Zheng Yusong Wu Fan Zhang Xinhao Yang Yi Cai Yu Wang Huazhong Yang Tsinghua University Beijing China Tsinghua University & VirtAI Tech Beijing China

ISBN: (纸本)9781450382182

With the ever-growing demands for online Artificial Intelligence (AI), the hardware virtualization support for deep learning accelerators is vital for providing AI capability in the cloud. Three basic features, multi-task, dynamic workload, and remote access, are fundamental for hardware virtualization. However, most of the deep learning accelerators do not support concurrent execution of multiple tasks. Besides, the SOTA multi-DNN scheduling algorithm for NN accelerators neither consider the multi-task concurrent execution and resources allocation for the multi-core DNN accelerators. Moreover, existing GPU virtualized solutions could introduce a huge remote access latency overhead, resulting in a severe system performance *** order to tackle these challenges, we propose 3M-AI, a Multi-task and Multi-core virtualization framework for Multi-fpga AI systems in the cloud. 3M-AI enables model parallelism on multi-fpga by optimizing data synchronization and movement between fpgas. 3M-AI exploits heuristic hardware resource allocation algorithm and accurate multi-core latency prediction model. 3M-AI significantly reduces the remote API access overhead to nearly 1%, and achieves better NN inference latency with a batch size 1 compared with GPU virtualization solutions.

关键词： virtualization cloud fpga deep learning

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APCNN: Explore Multi-Layer Cooperation for CNN Optimization and Acceleration on fpga 21

APCNN: Explore Multi-Layer Cooperation for CNN Optimization ...

引用

The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Beilei Jiang Xianwei Cheng Sihai Tang Xu Ma Zhaochen Gu Hui Zhao Song Fu University of North Texas Denton TX USA

ISBN: (纸本)9781450382182

In this paper, we introduce APCNN, which explores algorithm-hardware co-design and provides a CNN acceleration framework with multi-layer cooperative optimization and customized design on fpga. In terms of the algorithm design, the pooling layer is moved before the non-linear activation function and normalization in APCNN, which we prove causes negligible accuracy loss; the pooling layer is then co-optimized with the convolutional layer by means of redundant multiplication elimination, local addition reuse, and global addition reuse. We further design a dedicated accelerator to take full advantage of convolutional-pooling cross-layer optimization to not only accelerate computation but also reduce on-off chip data communication on fpga. We demonstrate that our novel APCNN can achieve 75% multiplication and 75% addition reduction in the best case. For on-off chip data communication, a max{Row,Col} /(Row x Col) percent of memory footprint can be eliminated, where Row and Col are the number of rows and columns in the activation feature map respectively. We have implemented a prototype of APCNN and evaluated its performance on LeNet-5 and VGG16 using both an accelerator-level cycle and energy model and an RTL implementation. Our experimental results show that APCNN achieves a 2.5× speedup and 4.7× energy efficiency compared with the dense CNN. (This research was supported in part by NSF grants CCF-1563750, OAC-2017564, and CNS-2037982.)

关键词： CNN acceleration fpga cross-layer optimization

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NPE: An fpga-based Overlay Processor for Natural Language Processing 21

NPE: An FPGA-based Overlay Processor for Natural Language Pr...

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Hamza Khan Asma Khan Zainab Khan Lun Bin Huang Kun Wang Lei He University of California Los Angeles Los Angeles CA USA University of California Irvine Irvine CA USA Stanford University Stanford CA USA Independent Researcher San Diego CA USA

ISBN: (纸本)9781450382182

In recent years, transformer-based models have shown state-of-the-art results for Natural Language Processing (NLP). In particular, the introduction of the BERT language model brought with it breakthroughs in tasks such as question answering and natural language inference, advancing applications that allow humans to interact naturally with embedded devices. fpga-based overlay processors have been shown as effective solutions for edge image and video processing applications, which mostly rely on low precision linear matrix operations. In contrast, transformer-based NLP techniques employ a variety of higher precision nonlinear operations with significantly higher frequency. We present NPE, an fpga-based overlay processor that can efficiently execute a variety of NLP models. NPE offers software-like programmability to the end user and, unlike fpga designs that implement specialized accelerators for each nonlinear function, can be upgraded for future NLP models without requiring reconfiguration. NPE can meet real-time conversational AI latency targets for the BERT language model with 4x lower power than CPUs and 6x lower power than GPUs. We also show NPE uses 3x fewer fpga resources relative to comparable BERT network-specific accelerators in the literature. NPE provides a cost-effective and power-efficient fpga-based solution for Natural Language Processing at the edge.

关键词： processor overlay machine learning accelerator BERT fpga nonlinear NLP

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AutoDSE: Enabling Software Programmers Design Efficient fpga Accelerators 21

AutoDSE: Enabling Software Programmers Design Efficient FPGA...

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The 2021 acm/sigda international symposium on field-programmable gate arrays

作者： Atefeh Sohrabizadeh Cody Hao Yu Min Gao Jason Cong University of California Los Angeles Los Angeles CA USA Falcon Computing Inc. Los Angeles CA USA University of California Los Angeles & Falcon Computing Inc. Los Angeles CA USA

ISBN: (纸本)9781450382182

Adopting fpga as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that fpgas are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS), accelerator designers still must manually perform code reconstruction and cumbersome parameter tuning to achieve the optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. We address this problem by incorporating an automated DSE framework - AutoDSE - that leverages bottleneck-guided gradient optimizer to systematically find a better design point. AutoDSE finds the bottleneck of the design in each step and focuses on high-impact parameters to overcome that, which is like the approach an expert would take. The experimental results show that AutoDSE is able to find the design point that achieves, on the geometric mean, 19.9x speedup over one CPU core for Machsuite and Rodinia benchmarks and 1.04x over the manually designed HLS accelerated vision kernels in Xilinx Vitis libraries yet with 26x reduction of their optimization pragmas.

关键词： high-level synthesis customized computing design automation

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HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing 19

HeteroCL: A Multi-Paradigm Programming Infrastructure for So...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Lai, Yi-Hsiang Chi, Yuze Hu, Yuwei Wang, Jie Yu, Cody Hao Zhou, Yuan Cong, Jason Zhang, Zhiru Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA Falcon Comp Solut Inc Santa Clara CA USA

ISBN: (纸本)9781450361378

With the pursuit of improving compute performance under strict power constraints, there is an increasing need for deploying applications to heterogeneous hardware architectures with accelerators, such as GPUs and fpgas. However, although these heterogeneous computing platforms are becoming widely available, they are very difficult to program especially with fpgas. As a result, the use of such platforms has been limited to a small subset of programmers with specialized hardware knowledge. To tackle this challenge, we introduce HeteroCL, a programming infrastructure composed of a Python-based domain-specific language (DSL) and an fpga-targeted compilation flow. The HeteroCL DSL provides a clean programming abstraction that decouples algorithm specification from three important types of hardware customization in compute, data types, and memory architectures. HeteroCL further captures the interdependence among these different customization techniques, allowing programmers to explore various performance/area/accuracy trade-offs in a systematic and productive manner. In addition, our framework produces highly efficient hardware implementations for a variety of popular workloads by targeting spatial architecture templates such as systolic arrays and stencil with dataflow architectures. Experimental results show that HeteroCL allows programmers to explore the design space efficiently in both performance and accuracy by combining different types of hardware customization and targeting spatial architectures, while keeping the algorithm code intact.

关键词： stencil domain-specific language fpga systolic array reconfigurable computing high-level synthesis multi-paradigm programming spatial architecture hardware accelerator python compiler

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Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud fpgas 19

Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud...

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acm/sigda international symposium on field-programmable gate arrays (fpga)

作者： Chen, Yao He, Jiong Zhang, Xiaofan Hao, Cong Chen, Deming Adv Digital Sci Ctr Singapore Singapore Univ Illinois Champaign IL USA

ISBN: (纸本)9781450361378

The efficacy and effectiveness of Convolutional Neural Networks (CNNs) have been proven in a wide range of machine learning applications. However, the high computational complexity of CNNs presents a critical challenge towards their broader adoption in real-time and power-efficient scenarios. fpgas are poised to take a significant role for high-performance and energy-efficient computation of CNNs for both mobile (e.g., UAVs, self-driving cars, and IoT devices) and cloud computing domains. However, implementing an effective CNN system onto fpgas efficiently remains problematic. The current cloud-based fpgas with unique design constraints and architectural characteristics further increase the challenges. To address these challenges, we propose a novel open-source automated tool chain called Cloud-DNN. Our tool chain takes trained CNN models specified in Caffe as input, performs a set of transformations, and maps the model to a cloud-based fpga. Cloud-DNN can significantly improve the overall design productivity of CNNs on fpgas while satisfying the emergent computational requirements. Our design provides an alternative solution compared to other cloud-based options (e.g., GPUs or TPUs) while offering flexible, and high performance DNN inferences. The unique features of Cloud-DNN include the optimizations with cloud-platform characteristics and the support of easier and streamlined implementation. Experimental results demonstrate up to 104.55x performance improvement when compared to CPU implementation and comparable usability, flexibility, and strong quality compared to other state-of-the-art DNN inference implementations on standalone fpgas.

关键词： DNN Accelerator fpga High-Level Synthesis Cloud Computing

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