检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,279 篇 会议
40 篇 期刊文献

馆藏范围

1,319 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

797 篇 工学
- 784 篇 计算机科学与技术...
- 349 篇 软件工程
- 281 篇 电气工程
- 254 篇 电子科学与技术（可...
- 130 篇 信息与通信工程
- 37 篇 动力工程及工程热...
- 34 篇 控制科学与工程
- 28 篇 机械工程
- 17 篇 生物工程
- 14 篇 仪器科学与技术
- 12 篇 建筑学
- 12 篇 土木工程
- 10 篇 生物医学工程（可授...
- 9 篇 冶金工程
- 8 篇 材料科学与工程（可...
- 7 篇 光学工程
- 7 篇 化学工程与技术
- 3 篇 农业工程
224 篇 理学
- 186 篇 数学
- 37 篇 物理学
- 20 篇 统计学（可授理学、...
- 19 篇 生物学
- 10 篇 系统科学
- 6 篇 化学
64 篇 管理学
- 51 篇 管理科学与工程(可...
- 35 篇 工商管理
- 14 篇 图书情报与档案管...
16 篇 经济学
- 16 篇 应用经济学
11 篇 法学
- 9 篇 社会学
3 篇 农学
- 3 篇 作物学
2 篇 教育学
1 篇 医学

主题

450 篇 fpga
237 篇 field programmab...
152 篇 field programmab...
27 篇 high-level synth...
25 篇 routing
25 篇 reconfigurable c...
22 篇 deep learning
22 篇 opencl
18 篇 hls
18 篇 hardware acceler...
17 篇 fpgas
16 篇 accelerator
15 篇 placement
14 篇 cnn
14 篇 machine learning
14 篇 convolutional ne...
12 篇 architecture
12 篇 optimization
12 篇 partial reconfig...
11 篇 technology mappi...

机构

19 篇 university of ca...
12 篇 tsinghua univers...
12 篇 fudan university
12 篇 imperial college...
11 篇 university of to...
10 篇 university of to...
9 篇 university of ce...
9 篇 university of so...
9 篇 peking universit...
8 篇 univ of californ...
7 篇 university of sc...
7 篇 univ of toronto ...
7 篇 epfl lausanne
7 篇 école polytechni...
7 篇 univ toronto dep...
7 篇 univ calif los a...
7 篇 nanyang technolo...
7 篇 tsinghua univ pe...
6 篇 univ british col...
6 篇 northeastern uni...

作者

37 篇 cong jason
26 篇 rose jonathan
22 篇 jason cong
17 篇 betz vaughn
15 篇 zhang zhiru
14 篇 chen deming
13 篇 ienne paolo
12 篇 chow paul
12 篇 wawrzynek john
11 篇 hauck scott
10 篇 dehon andré
10 篇 luk wayne
10 篇 prasanna viktor ...
10 篇 langhammer marti...
9 篇 jinmei lai
9 篇 anderson jason h...
9 篇 wilton steven j....
9 篇 schmit herman
9 篇 jonathan rose
9 篇 constantinides g...

语言

1,300 篇 英文
19 篇 其他

检索条件"任意字段=ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004"

共 1319 条记录，以下是51-60 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Towards Agile DNN Accelerator Design Using Incremental Synthesis on fpgas 22

Towards Agile DNN Accelerator Design Using Incremental Synth...

引用

2022 acm/sigda international symposium on field-programmable gate arrays, fpga 2022

作者： Xiao, Qingcheng Liang, Yun Peking University Beijing China

ISBN: (纸本)9781450391498

Hardware-software co-design is the new trend for deep neural network and fpga accelerator development, which iteratively revises and tunes the full system. The bottleneck of the approach lies in the time-consuming hardware synthesis. In this paper, we propose an incremental synthesis framework Acoda to rapidly design DNN accelerators on fpgas. Based on the observation that most revisions to DNNs are minor and local, Acoda reuses existing hardware modules and incrementally modifies the accelerator. It first detects the software revisions using a graph edit distance algorithm. Then, it maps the software revisions to hardware revisions through a multi-level reuse hierarchy. As a result, Acoda speeds up the design process by 9.31X to 34.17X and achieves performance results comparable to off-the-shelf accelerators. © 2022 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

fpga 2024 Chairs' Welcome

FPGA 2024 - Proceedings of the 2024 ACM/SIGDA International ...

引用

fpga 2024 - Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays 2024年 iii页

作者： Zhang, Zhiru Putnam, Andrew Cornell University United States Microsoft United States

来源：评论

学校读者我要写书评

暂无评论

hAP: A Spatial-von Neumann Heterogeneous Automata Processor with Optimized Resource and IO Overhead on fpga 23

hAP: A Spatial-von Neumann Heterogeneous Automata Processor ...

引用

31st acm/sigda international symposium on field programmable gate arrays (fpga)

作者： Wang, Xuan Gong, Lei Cao, Jing Lou, Wenqi Wang, Weiya Wang, Chao Zhou, Xuehai Univ Sci & Technol China Hefei Peoples R China Boston Univ Boston MA 02215 USA

ISBN: (纸本)9781450394178

Regular expression (REGEX) matching tasks drive much research on automata processors (AP). Among them, the von Neumann AP can efficiently utilize on-chip memory to process the Deterministic Finite Automata (DFA), but it is limited to small REGEX sets due to the DFA's state explosion problem. For large REGEX sets, the spatial AP based on Nondeterministic Finite Automaton (NFA) is the mainstream choice. However, there are two problems with previous fpga-based spatial AP. First, it cannot obtain a balanced fpga resource usage (LUT and BRAM), which easily leads to resource shortage. Second, to compress the report output data of large REGEX sets, it uses dynamic report compression, which not only consumes a lot of fpga resources but also limits performance. This paper optimizes the resource and IO overhead of spatial AP. First, noticing the resource optimization ability of the von Neumann AP, we propose the flex-hybrid-FA algorithm to generate small hybrid-FAs (an NFA/DFA hybrid model) and further propose the Spatial-von Neumann Heterogeneous AP to deploy hybridFA. Under the constraints of the flex-hybrid-FA algorithm, we can obtain balanced and efficient fpga resource usage. Second, we propose High-Efficient Automata Report Compression (HEARC) with a compression ratio of up to 5.5-47.6x, which can thoroughly release the performance from IO congestion, and consumes less fpga resource compared to previous dynamic report compression approaches. As far as we know, this is the first work to deploy large REGEX sets on low-cost small-scale fpgas (e.g. Xilinx XCZU3CG). The experimental results show that compared to the previous fpga-based APs, we save 4.0-6.6x power consumption and improve 2.75.9x energy efficiency.

关键词： Automata Processor Hybrid-FA Automata Report Compression

来源：评论

学校读者我要写书评

暂无评论

fpga 2017 - Proceedings of the 2017 acm/sigda international symposium on field-programmable gate arrays

FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International ...

引用

2017 acm/sigda international symposium on field-programmable gate arrays, fpga 2017

ISBN: (纸本)9781450343541

The proceedings contain 32 papers. The topics discussed include: the role of fpgas in deep learning;accelerating binarized convolutional neural networks with software-programmable fpgas;improving the performance of OpenCL-based fpga accelerator for convolutional neural network;frequency domain acceleration of convolutional neural networks on CPU-fpga shared memory system;FINN: a framework for fast, scalable binarized neural network inference;quality-time tradeoffs in component-specific mapping: how to train your dynamically reconfigurable array of gates with outrageous network-delays;synchronization constraints for interconnect synthesis;automatic construction of program-optimized fpga memory networks;a parallelized iterative improvement approach to area optimization for LUT-based technology mapping;a new approach to automatic memory banking using trace-based address mining;dynamic hazard resolution for pipelining irregular loops in high-level synthesis;and secure function evaluation using an fpga overlay architecture.

关键词：

来源：评论

学校读者我要写书评

暂无评论

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die fpgas 23

FADO: Floorplan-Aware Directive Optimization for High-Level ...

引用

31st acm/sigda international symposium on field programmable gate arrays (fpga)

作者： Du, Linfeng Liang, Tingyuan Sinha, Sharad Xie, Zhiyao Zhang, Wei Hong Kong Univ Sci & Technol Kowloon Hong Kong Peoples R China Indian Inst Technol Goa Ponda Goa India

ISBN: (纸本)9781450394178

Multi-die fpgas are widely adopted to deploy large-scale hardware accelerators. Two factors impede the performance optimization of high-level synthesis (HLS) designs implemented on multi-die fpgas. On the one hand, the long net delay due to nets crossing die-boundaries results in an NP-hard problem to properly floorplan and pipeline an application. On the other hand, traditional automated searching flow for HLS directive optimizations targets single-die fpgas, and hence, it cannot consider the resource constraints on each die and the timing issue incurred by the die-crossings. Further, it leads to an excessively long runtime to legalize the floorplanning of HLS designs generated under each group of configurations during directive optimization due to the large design scale. To co-optimize the directives and floorplan of HLS designs on multi-die fpgas, we propose the FADO framework, which formulates the directive-floorplan co-search problem based on the multi-choice multi-dimensional bin-packing and solves it using an iterative optimization flow. For each step of directive optimization, a latency-bottleneck-guided greedy algorithm searches for more efficient directive configurations. For floorplanning, instead of repetitively incurring global floorplanning algorithms, we implement a more efficient incremental floorplan legalization algorithm. It mainly applies the worst-fit strategy from the online bin-packing algorithm to balance the floorplan, together with an offline best-fit-decreasing re-packing step to compact the floorplan, followed by pipelining of the long wires crossing die-boundaries. Through experiments on a set of HLS designs mixing dataflow and non-dataflow kernels, FADO not only well-automates the co-optimization and finishes within 693X similar to 4925X shorter runtime, compared with DSE assisted by global floorplanning, but also yields an improvement of 1.16X similar to 8.78X in overall workflow execution time after implementation on the Xilinx Alveo

关键词： High-Level Synthesis Design Space Exploration Multi-Die fpga Directive Optimization Floorplanning

来源：评论

学校读者我要写书评

暂无评论

How to shrink my fpgas - Optimizing Tile Interfaces and the Configuration Logic in FABulous fpga Fabrics 22

How to shrink my FPGAs - Optimizing Tile Interfaces and the ...

引用

2022 acm/sigda international symposium on field-programmable gate arrays, fpga 2022

作者： Chung, King Lok Dao, Nguyen Yu, Jing Koch, Dirk Computer Science University of Manchester Manchester United Kingdom

ISBN: (纸本)9781450391498

Commercial fpgas from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (=speed), and power consumption together. This paper is dedicated to improving the physical implementation of fpga tiles and the configuration storage in SRAM fpgas. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous fpga framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity. Our optimizations consider all tiles and we propose a flow that resolves dependencies between the CLBs and other tiles. Moreover, we will show that frame-based reconfiguration is, in almost all cases, better than shift register configuration. © 2022 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

An fpga-based RNN-T inference accelerator with PIM-HBM 22

An FPGA-based RNN-T inference accelerator with PIM-HBM

引用

2022 acm/sigda international symposium on field-programmable gate arrays, fpga 2022

作者： Kang, Shin-Haeng Lee, Sukhan Kim, Byeongho Kim, Hweesoo Sohn, Kyomin Kim, Nam Sung Lee, Eojin Samsung Electronics Hwaseong Korea Republic of Seoul National University Seoul Korea Republic of Inha University Incheon Korea Republic of

ISBN: (纸本)9781450391498

In this paper, we implemented a world-first RNN-T inference accelerator using fpga with PIM-HBM that can multiply the internal bandwidth of the memory. The accelerator offloads matrix-vector multiplication (GEMV) operations of LSTM layers in RNN-T into PIM-HBM, and PIM-HBM reduces the execution time of GEMV significantly by exploiting HBM internal bandwidth. To ensure that the memory commands are issued in a pre-defined order, which is one of the most important constraints in exploiting PIM-HBM, we implement a direct memory access (DMA) module and change configuration of the on-chip memory controller by utilizing the flexibility and reconfigurability of the fpga. In addition, we design the other hardware modules for acceleration such as non-linear functions (i.e., sigmoid and hyperbolic tangent), element-wise operation, and ReLU module, to operate these compute-bound RNN-T operations on fpga. For this, we prepare FP16 quantized weight and MLPerf input datasets, and modify the PCIe device driver and C++ based control codes. On our evaluation, our accelerator with PIM-HBM reduces the execution time of RNN-T by 2.5 × on average with 11.09% reduced LUT size and improves energy efficiency up to 2.6 × compared to the baseline. © 2022 acm.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

Quality-driven Design Methodology for PUFs in fpgas for Secure IoT 24

Quality-driven Design Methodology for PUFs in FPGAs for Secu...

引用

24th international symposium on Quality Electronic Design (ISQED)

作者： Wang, Xiangyun Song, Yicheng Prakash, Katyayani Zilic, Zeljko Langsetmo, Tomas McGill Univ Montreal PQ Canada KNOX Ind Inc Montreal PQ Canada

ISBN: (纸本)9798350334753

The emergence of Internet of Things (IoT) has placed strong emphasis on security. Physical Unclonable Functions (PUFs) are a promising low-cost security solution for IoT. Since field-programmable gate arrays (fpgas) are more trusted than custom Integrated Circuits (ICs) in building secure systems, implementing PUFs in fpgas is appealing. In this paper, we propose a methodology for improving the quality of delay-based PUFs on fpgas. With our method, an asymmetric delay-based PUF has been predictably designed for temperature- and aging-independent operation. Furthermore, the resistance to modeling attacks is built into the design.

关键词： Physical Unclonable Function (PUF) Internet-of-Things (IoT) field-programmable gate Array (fpga) Hardware Security Design Methodology

来源：评论

学校读者我要写书评

暂无评论

Accounting for Floorplan Irregularity and Configuration Dependence in fpga Routing Delay Models 24

Accounting for Floorplan Irregularity and Configuration Depe...

引用

24th international symposium on Quality Electronic Design (ISQED)

作者： Barajas, Gabriel Greene, Jonathan W. Li, Fei Tandon, James Microchip San Jose CA 95134 USA Cambios Comp LLC Palo Alto CA USA Calif State Univ East Bay Hayward CA USA

ISBN: (纸本)9798350334753

Accurate delay estimates for a user application implemented in a field-programmable gate Array (fpga) are essential for a quality fpga timing flow and to avoid leaving performance on the table. fpga inter-cluster routing consists of wire segments of a limited number of types which repeat in a somewhat regular pattern, interconnected by configurable muxes. The delay at any fanout of a segment can be significantly impacted by configuration-dependent capacitive loading related to other fanouts. Also, the insertion of RAM and math blocks into the fpga floorplan introduces irregular stretching of the wire segments, altering their delays. We explain why and how commercial fpga software typically employs a parameterized model for the delay at each fanout of a segment, based on the configuration and the irregularities present, with the parameters determined by fitting SPICE simulation data for a representative sample of cases. We propose incorporating readily-computed common path resistance values into the model. This enables high accuracy with fewer parameters and without the large amounts of SPICE data that would otherwise be required to explore interactions between floorplan irregularities and the set of active fanouts. In combination with other features of our models, errors in segment delay are reduced by almost half.

关键词： field-programmable gate arrays fpgas delay estimation Elmore delay common path resistance

来源：评论

学校读者我要写书评

暂无评论

Online Training from Streaming Data with Concept Drift on fpgas 24

Online Training from Streaming Data with Concept Drift on FP...

引用

24th international symposium on Quality Electronic Design (ISQED)

作者： Roorda, Esther Wilton, Steven J. E. Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9798350334753

In dynamic environments, the inputs to machine learning models may exhibit statistical changes over time, through what is called concept drift. Incremental training can allow machine learning models to adapt to changing conditions and maintain high accuracy by continuously updating network parameters. In the context of fpga-based accelerators however, online incremental learning is challenging due to resource and communication constraints, as well as the absence of labelled training data. These challenges have not been fully evaluated or addressed in existing research. In this paper, we present and evaluate strategies for performing incremental training on streaming data with concept drift on fpga-based platforms. We first present fpga-based implementations of existing training algorithms to demonstrate the viability of online training with concept shift and to evaluate design tradeoffs. We then propose a technique for online training without labelled data and demonstrate its potential in the context of fpga-based hardware acceleration.

关键词： field programmable gate arrays (fpga)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共132页 << < 2 3 4 5 6 7 8 9 10 11 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：