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fpga 2022 Chairs' Welcome

FPGA 2022 - Proceedings of the 2022 ACM/SIGDA International ...

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fpga 2022 - Proceedings of the 2022 acm/sigda international symposium on field-programmable gate arrays 2022年 III页

作者： Adler, Michael Ienne, Paolo Intel United States EPFL Switzerland

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Efficient fpga modular multiplication implementation 21

Efficient fpga modular multiplication implementation

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Langhammer, Martin Pasca, Bogdan Intel Corporation United Kingdom Intel Corporation France

ISBN: (纸本)9781450382182

Barrett's algorithm is the most commonly known method of performing a modular multiplication, which is the core of many modern encryption algorithms such as RSA. Barrett's algorithm requires an accurate quotient estimation which in turn requires accurate multiplications. These multiplications operating on word sizes of thousands of bits are particularly expensive to implement in fpgas, requiring many hundreds or even thousands of embedded DSP components along with large amounts of logic and routing. In this work we show that approximate quotient estimates as results of aggressive multiplier truncations can significantly reduce implementation cost. The looser modified Barrett's output [0;YM) is reduced to [0;M) using a shallow reduction technique based on table lookups and wide additions, taking advantage of new techniques which have recently been introduced for fpga. We first use these techniques to develop an improved standard Barrett's implementation for 1024b modular multiplication, followed by our approximate method which reduces logic cost in the LSB truncated multiplier by approximately 10%. The effect is more pronounced for very large word sizes, where our relaxed error bounds in the LSB truncated multiplication can reduce the number of operations by 20%. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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An Empirical Comparision of LLM-based Hardware Design and High-level Synthesis 25

An Empirical Comparision of LLM-based Hardware Design and Hi...

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Proceedings of the 2025 acm/sigda international symposium on field programmable gate arrays

作者： Fan Cui Youwei Xiao Kexing Zhou Yun Liang School of Integrated Circuits Peking University Beijing China

ISBN: (纸本)9798400713965

field-programmable gate arrays (fpgas) are increasingly used for accelerating diverse applications due to their reconfigurability and ability to implement custom hardware architectures. However, programming fpgas remains challenging, traditionally relying on low-level Hardware Description Languages (HDLs) like Verilog, which are intricate and time-consuming. High-Level Synthesis (HLS) tools, such as Vitis HLS, have emerged to address these issues by allowing hardware functionality description in high-level languages like C/C++, but they come with their own limitations, including less efficient hardware implementations, delay overhead caused by conservative scheduling strategies, and unpredictable solutions due to semantic differences between software and *** paper explores the potential of Large Language Models (LLMs) in fpga design, particularly for generating complex Verilog kernels. We present a novel approach that guides LLMs to generate synthesizable and efficient Verilog code for complex fpga kernels. Our method addresses key challenges in LLM-based hardware design. Through a case study on the PolyBench suite, we demonstrate that our LLM-guided approach can generate HDL implementations that surpass HLS tools in performance and resource utilization. The experimental results show that our approach reduces latency by an average of 28.88% compared to HLS, with a maximum reduction of 66.94% in pipelined designs and an average reduction of 8.41%, peaking at 55.76% in sequential stages. Furthermore, it decreases LUT usage by an average of 25.18% and flip-flop usage by 57.23% compared to HLS.

关键词： fpga

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MOCHA: Multinode cost optimization in heterogeneous clouds with accelerators 21

MOCHA: Multinode cost optimization in heterogeneous clouds w...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Zhou, Peipei Sheng, Jiayi Yu, Cody Hao Wei, Peng Wang, Jie Wu, Di Cong, Jason University of Pittsburgh United States University of California Los Angeles United States Microsoft Amazon Web Services Google Facebook

ISBN: (纸本)9781450382182

fpgas have been widely deployed in public clouds, e.g., Amazon Web Services (AWS) and Huawei Cloud. However, simply offloading accelerated kernels from CPU hosts to PCIe-based fpgas does not guarantee out-of-pocket cost savings in a pay-as-you-go public cloud. Taking Genome Analysis Toolkit (GATK) applications as case studies, although the adoption of fpgas reduces the overall execution time, it introduces 2.56× extra cost, due to insufficient application-level speedup by Amdahl's law. To optimize the out-of-pocket cost while keeping high speedup and throughput, we propose Mocha framework as a distributed runtime system to fully utilize the accelerator resource by accelerator sharing and CPU-fpga partial task offloading. Evaluation results on Haplotype Caller (HTC) and Mutect2 in GATK show that on AWS, Mocha saves on the application cost by 2.82x for HTC, 1.06x for Mutect2 and on Huawei Cloud by 1.22x, 1.52x respectively than straightforward CPU-fpga integration solution with less than 5.1% performance overhead. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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HBM connect: High-performance hls interconnect for fpga hbm 21

HBM connect: High-performance hls interconnect for fpga hbm

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Choi, Young-Kyu Chi, Yuze Qiao, Weikang Samardzic, Nikola Cong, Jason Department of Computer Science University of California Los Angeles United States

ISBN: (纸本)9781450382182

With the recent release of High Bandwidth Memory (HBM) based fpga boards, developers can now exploit unprecedented external memory bandwidth. This allows more memory-bounded applications to benefit from fpga acceleration. However, fully utilizing the available bandwidth may not be an easy task. If an application requires multiple processing elements to access multiple HBM channels, we observed a significant drop in the effective bandwidth. The existing high-level synthesis (HLS) programming environment had limitation in producing an efficient communication architecture. In order to solve this problem, we propose HBM Connect, a high-performance customized interconnect for fpga HBM board. Novel HLS-based optimization techniques are introduced to increase the throughput of AXI bus masters and switching elements. We also present a high-performance customized crossbar that may replace the built-in crossbar. The effectiveness of HBM Connect is demonstrated using Xilinx's Alveo U280 HBM board. Based on bucket sort and merge sort case studies, we explore several design spaces and find the design point with the best resource-performance trade-off. The result shows that HBM Connect improves the resource-performance metrics by 6.5X-211X. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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Tensor slices to the rescue: Supercharging ml acceleration on fpgas 21

Tensor slices to the rescue: Supercharging ml acceleration o...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Arora, Aman Mehta, Samidh Betz, Vaughn John, Lizy K. University of Texas at Austin AustinTX United States Birla Institute of Technology and Science Pilani Goa India University of Toronto TorontoON Canada

ISBN: (纸本)9781450382182

fpgas are well-suited for accelerating deep learning (DL) applications owing to the rapidly changing algorithms, network architectures and computation requirements in this field. However, the generic building blocks available on traditional fpgas limit the acceleration that can be achieved. Many modifications to fpga architecture have been proposed and deployed including adding specialized artificial intelligence (AI) processing engines, adding support for IEEE half-precision (fp16) math in DSP slices, adding hard matrix multiplier blocks, etc. In this paper, we describe replacing a small percentage of the fpga's programmable logic area with Tensor Slices. These slices are arrays of processing elements at their heart that support multiple tensor operations, multiple dynamically-selectable precisions and can be dynamically fractured into individual adders, multipliers and MACs (multiply-and-accumulate). These tiles have a local crossbar at the inputs that helps with easing the routing pressure caused by a large slice. By spending ∼3% of fpga's area on Tensor Slices, we observe an average frequency increase of 2.45x and average area reduction by 0.41x across several ML benchmarks, including a TPU-like design, compared to an Intel Agilex-like baseline fpga. We also study the impact of spending area on Tensor slices on non-ML applications. We observe an average reduction of 1% in frequency and an average increase of 1% in routing wirelength compared to the baseline, across the non-ML benchmarks we studied. Adding these ML-specific coarse-grained hard blocks makes the proposed fpga a much efficient hardware accelerator for ML applications, while still keeping the vast majority of the real estate on the fpga programmable at fine-grain. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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Top-down physical design of soft embedded fpga fabrics 21

Top-down physical design of soft embedded fpga fabrics

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Mohan, Prashanth Atli, Oguz Kibar, Onur Zackriya, Mohammed Pileggi, Larry Mai, Ken Department of Electrical and Computer Engineering Carnegie Mellon University PittsburghPA United States

ISBN: (纸本)9781450382182

In recent years, IC reverse engineering and IC fabrication supply chain security have grown to become significant economic and security threats for designers, system integrators, and end customers. Many of the existing logic locking and obfuscation techniques have shown to be vulnerable to attack once the attacker has access to the design netlist either through reverse engineering or through an untrusted fabrication facility. We introduce soft embedded fpga redaction, a hardware obfuscation approach that allows the designer substitute security-critical IP blocks within a design with a synthesizable efpga fabric. This method fully conceals the logic and the routing of the critical IP and is compatible with standard ASIC flows for easy integration and process portability. To demonstrate efpga redaction, we obfuscate a RISC-V control path and a GPS P-code generator. We also show that the modified netlists are resilient to SAT attacks with moderate VLSI overheads. The secure RISC-V design has 1.89x area and 2.36x delay overhead while the GPS design has 1.39x area and negligible delay overhead when implemented on an industrial 22nm FinFET CMOS process. © 2021 acm.

关键词： field programmable gate arrays (fpga)

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An fpga-based 7-ENOB 600 msample/s adc without any external components 21

An FPGA-based 7-ENOB 600 msample/s adc without any external ...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Leuenberger, Lukas Amiet, Dorian Wei, Tao Zbinden, Paul OST-Eastern Switzerland University of Applied Sciences Imes Institute for Microelectronics and Embedded Systems Rapperswil Switzerland University of Rhode Island Department of Electrical Computer and Biomedical Engineering Kingston United States

ISBN: (纸本)9781450382182

Analog to digital converters (ADCs) are indispensable nowadays. Analog signals are digitized earlier and earlier in the processing chain to reduce the need for complex analog signal processing. For this reason, ADCs are often integrated directly into field-programmable gate arrays (fpga) or microprocessors. However, such ADCs are designed for a specific set of requirements with limited flexibility. In this paper, a new structure of an fpga-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured. Only fpga-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC. Considering the very high number of digital I/O ports available in today's fpga systems, this enables the construction of a massive and powerful ADC array directly on a standard fpga. The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. The differential nonlinearity (DNL) ranges from-0.9 to 0.9 bit, and the integral nonlinearity (INL) is in the range between-1.1 and 0.9 bit. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3. © 2021 acm.

关键词： Signal processing

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AutoSA: A polyhedral compiler for high-performance systolic arrays on fpga 21

AutoSA: A polyhedral compiler for high-performance systolic ...

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2021 acm/sigda international symposium on field-programmable gate arrays, fpga 2021

作者： Wang, Jie Guo, Licheng Cong, Jason University of California Los Angeles United States

ISBN: (纸本)9781450382182

While systolic array architectures have the potential to deliver tremendous performance, it is notoriously challenging to customize an efficient systolic array processor for a target application. Designing systolic arrays requires knowledge for both high-level characteristics of the application and low-level hardware details, thus making it a demanding and inefficient process. To relieve users from the manual iterative trial-and-error process, we present AutoSA, an end-to-end compilation framework for generating systolic arrays on fpga. AutoSA is based on the polyhedral framework, and further incorporates a set of optimizations on different dimensions to boost performance. An efficient and comprehensive design space exploration is performed to search for high-performance designs. We have demonstrated AutoSA on a wide range of applications, on which AutoSA achieves high performance within a short amount of time. As an example, for matrix multiplication, AutoSA achieves 934 GFLOPs, 3.41 TOPs, and 6.95 TOPs in floating point, 16-bit and 8-bit integer data types on Xilinx Alveo U250. © 2021 acm.

关键词： Systolic arrays

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AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based fpga Accelerator 24

AutoHammer: Breaking the Compilation Wall Between Deep Neura...

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Proceedings of the 2024 acm/sigda international symposium on field programmable gate arrays

作者： Kai Qian Zheng Liu Yinqiu Liu Haodong Lu Zexu Zhang Ruiqiu Chen Kun Wang Fudan University Shanghai China Nanyang Technological University Singpore Singapore Fudan University Shanghaii China

ISBN: (纸本)9798400704185

field-programmable gate Array (fpga) has shown great potential in accelerating Deep Neural Networks (DNNs) due to its characteristics of programmability and high power efficiency. In address the compilation challenges between DNNs and fpga, we propose AutoHammer, an automated compiler for mapping DNNs to different fpgas. Specifically, AutoHammer leverages overlay techniques to enable fast and effective implementation. Moreover, three enablers are integrated into AutoHammer. First, the Model Translator optimizes the topology and predicts a DNN's results based on different hardware configurations, built on top of a topology-based representation of DNNs. Second, the Instruction Generator generates pipeline data streams in various fpga resource configurations by manipulating the instruction set at the upper level rapidly. Last, we realize the End-to-end Optimization, moving the whole computational processes onto the fpga. Extensive experimental results show that AutoHammer improves great deployment efficiency when validated by 14 types of DNN models on 3 companies' (Xilinx, Fudan Micro, and Pango Micro) mainstream fpga chips.

关键词： compiler deep neural networks field-programmable gate array (fpga)

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