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hardware/software partitioning for multi-function systems 97

Hardware/software partitioning for multi-function systems

引用

Proceedings of the 1997 IEEE/acm international conference on Computer-aided design

作者： Asawaree Kalavade P. A. Subrahmanyam DSP and VLSI Systems Research Dept. Bell Labs Holmdel NJ

ISBN: (纸本)9780818682001

We are interested in optimizing the design of multi-function embedded systems that run a pre-specified set of applications, such as multi-standard audio/video codecs and multi-system phones. Such systems usually have stringent performance constraints and tend to have mixed hardware-software implementations. The current state of the art in the hardware/software codesign of such systems is to design for each application separately. This often leads to application-specific sub-optimal decisions and inconsistent mappings of common nodes in different applications. We use these as the guiding principles to formulate, as a codesign problem, the design and synthesis of an efficient hardware-software implementation for a multi-function embedded system. Our solution methodology is to first identify nodes that represent similar functionality across different applications. Such "common" nodes are characterized by several metrics. These metrics are quantified and used by a hardware/software partitioning tool to map common nodes to the same resource as far as possible. We demonstrate how this is achieved by modifying a traditional partitioning algorithm (GCLP) used to partition single applications. The overall result of the system-level partitioning process is (1) a hardware or software mapping and (2) a schedule for execution for each node within the application set. On an example set consisting of three video applications, we show that the solution obtained by the use of our method is 38% smaller than that obtained when each application is considered independently.

关键词： core-based design

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Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system 97

Real time analysis and priority scheduler generation for har...

引用

Proceedings of the 1997 IEEE/acm international conference on Computer-aided design

作者： Vincent J. Mooney, III Giovanni De Micheli Computer Systems Laboratory Stanford University Gates Computer Science Building Stanford CA

ISBN: (纸本)9780818682001

We present a tool, called Clara, that performs real-time analysis and priority assignment for software tasks in a mixed hardware-software system with a custom run-time scheduler. We start from a system described in tasks/threads consisting of hardware specified in Verilog and software specified in C. We obtain the worst case execution time for each individual task. Then, based on the control flow of the application, Clara uses a dynamic programmming algorithm to automatically find optimal priorities for the software tasks assuming no interrupts. Assuming the set of software tasks runs on a microprocessor in a target architecture using a template we provide for the priority scheduler and interrupt code, Clara then finds the worst case execution time for the application with interrupts allowed. Thus, this tool brings real-time analysis to a system level for a particular run-time system. Clara helps a designer minimize the worst case execution time of a mixed hardware-software application.

关键词： hardware-software codesign

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hardware/software partitioning for multi-function systems

Hardware/software partitioning for multi-function systems

引用

IEEE international conference on Computer-Aided Design

作者： Kalavade Subrahmanyam DSP and VLSI Systems Research Department Bell Laboratories Holmdel NJ USA

We are interested in optimizing the design of multi-function embedded systems that run a pre-specified set of applications, such as multi-standard audio/video codecs and multi-system phones. Such systems usually have stringent performance constraints and tend to have mixed hardware-software implementations. The current stare of the art in the hardware/software codesign of such systems is to design for each application separately. This often leads to application-specific sub-optimal decisions and inconsistent mappings of common nodes in different applications. We use these as the guiding principles to formulate, as a codesign problem, the design and synthesis of an efficient hardware-software implementation for a multi-function embedded system. Our solution methodology is to first identify nodes that represent similar functionality across different applications. Such "common" nodes are characterized by several metrics. These metrics are quantified and used by a hardware/software partitioning tool to map common nodes to the same resource as far as possible. We demonstrate how this is achieved by modifying a traditional partitioning algorithm (GCLP) used to partition single applications. The overall result of the system-level partitioning process is (1) a hardware or software mapping and (2) a schedule for execution for each node within the application set. On an example set consisting of three video applications, we show that the solution obtained by the use of our method is 38% smaller than that obtained when each application is considered independently.

关键词： Real time systems

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Java as a specification language for hardware-software systems 97

Java as a specification language for hardware-software syste...

引用

Proceedings of the 1997 IEEE/acm international conference on Computer-aided design

作者： Rachid Helaihel Kunle Olukotun Computer Systems Laboratory Stanford University Stanford CA

ISBN: (纸本)9780818682001

The specification language is a critical component of the hardware-software co-design process since it is used for functional validation and as a starting point for hardware- software partitioning and co-synthesis. This paper pro poses the Java programming language as a specification language for hardware-software systems. Java has several characteristics that make it suitable for system specification. However, static control and dataflow analysis of Java programs is problematic because Java classes are dynamically linked. This paper provides a general solution to the problem of statically analyzing Java programs using a technique that pre-allocates most class instances and aggressively resolve memory aliasing using global analysis. The output of our analysis is a control dataflow graph for the input specification. Our results for sample designs show that the analysis can extract fine to coarse-grained concurrency for subsequent hardware-software partitioning and co-synthesis steps of the hardware-software co- design process to exploit.

关键词： hardware-software co-design

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software synthesis through task decomposition by dependency analysis 96

Software synthesis through task decomposition by dependency ...

引用

Proceedings of the 1996 IEEE/acm international conference on Computer-aided design

作者： Youngsoo Shin Kiyoung Choi School of Electrical Engineering Seoul National University Seoul Korea 151-742

ISBN: (纸本)9780818675973

Latency tolerance is one of main problems of software synthesis in the design of hardware-software mixed systems. This paper presents a methodology for speeding up systems through latency tolerance which is obtained by decomposition of tasks and generation of an efficient scheduler. The task decomposition process focuses on the dependency analysis of system i/o operations. Scheduling of the decomposed tasks is performed in a mixed static and dynamic fashion. Experimental results show the significance of our approach.

关键词： scheduler CDFG dependency software synthesis thread

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MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems 97

MOGAC: a multiobjective genetic algorithm for the co-synthes...

引用

Proceedings of the 1997 IEEE/acm international conference on Computer-aided design

作者： Robert P. Dick Niraj K. Jha Department of Electrical Engineering Princeton University Princeton New Jersey

ISBN: (纸本)9780818682001

In this paper, we present a hardware-software co-synthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. MOGAC synthesizes real-time heterogeneous distributed architectures using an adaptive multiobjective genetic algorithm that can escape local minima. Price and power consumption are optimized while hard real-time constraints are met. MOGAC places no limit on the number of hardware or software processing elements in the architectures it synthesizes. Our general model for bus and point-to-point communication links allows a number of link types to be used in an architecture. Application-specific integrated circuits consisting of multiple processing elements are modeled. Heuristics are used to tackle multi-rate systems, as well as systems containing task graphs whose hyperperiods are large relative to their periods. The application of a multiobjective optimization strategy allows a single co-synthesis run to produce multiple designs which trade off different architectural features. Experimental results indicate that MOGAC has advantages over previous work in terms of solution quality and running time.

关键词： co-design

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Transformational partitioning for co-design of multiprocessor systems 97

Transformational partitioning for co-design of multiprocesso...

引用

Proceedings of the 1997 IEEE/acm international conference on Computer-aided design

作者： Gilberto Fernandes Marchioro Jean-Marc Daveau Ahmed Amine Jerraya System-Level Synthesis Group TIMA/INPG - Grenoble France

ISBN: (纸本)9780818682001

This paper presents the underlying methodology of Cosmos, an interactive approach for hardware/software co-design capable of handling multiprocessor systems and distributed architectures. The approach covers the co-design process through a set of user guided transformations allowing semi-automatic partitioning. The transformations are based on a powerful set of primitives for functional partitioning, structural reorganization and communication transformation. It leads to a fast transformation of a system-level specification into an architecture with a short design time and fast exploration of design space. The application of this approach is illustrated using several design examples starting from a system-level specification given in SDL to a distributed hardware/software architecture described in C/VHDL. We show that the use of transformational approach allows: Application of the expertise of the designer during partitioning ; - the user to understand the results of the co-design process ; the process to take into account partial existing solutions ; - large design space exploration ; the designer to start from a very high-level specification language of the system to be designed.

关键词： hardware/software co-design

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Design for testability: today and in the future

Design for testability: today and in the future

引用

international conference on VLSI Design

作者： T.W. Williams IBM Technology Products Boulder CO USA

Summary form only given. The author reviews the current techniques with a particular emphasis on today's Scan Designs. This entails distinguishing the differences between scan techniques, since all scans are not created equal! From this point the Testability Standards are discussed; these include the Boundary Scan activities and the Analog activities. Fault models are taking on more robust attributes, since the Stuck-At-Fault is necessary but not sufficient in today's technologies. The Delay Fault models are discussed with a comparison between a model which increases exponentially with gate count (Path Delay Fault) and one which increases linearly with gate count (Gate Delay Fault). Clearly, self-test is taking on an ever more important role which impacts both manufacturing testing and field system testing. The popular self-testing design techniques are shown. The interaction of testing and synthesis is discussed with a view on delay. Finally, the role of testing is explored in the new design environments which includes hardware and software codesign.

关键词： Design for testability Automatic testing Built-in self-test Delay Circuit testing Computer Society Books Logic testing system testing Very large scale integration

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Rapid prototyping of reconfigurable coprocessors

Rapid prototyping of reconfigurable coprocessors

引用

international conference on Application-Specific systems, Architectures and Processors

作者： Narasimhan, N Srinivasan, V Vootukuru, M Walrath, J Govindarajan, S Vemuri, R UNIV CINCINNATI DEPT ECECSLAB DIGITAL DESIGN ENVIRONMCINCINNATIOH 45221

ISBN: (纸本)081867542X

We describe the process of hardware-software codesign of a JPEG-like still image compression system. The hardware components are targeted to execute on a reconfigurable hardware coprocessor which communicates with a host computer that executes all the software tasks. Central to our codesign methodology is the usage of software profiling, high-level estimation and synthesis tools. We describe the process of trade-off analysis and hardware task selection in detail. We present detailed experimental results gathered throughout the codesign process.

关键词： Coprocessors rapid prototyping on line data service task selection hardware/software co-design compression system configurability Computer hardware JPEG Still images reconfigurable hardware

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Model refinement for hardware-software codesign

Model refinement for hardware-software codesign

引用

European Design and Test conference

作者： Gong, J Gajski, DD Bakshi, S UNIV CALIF IRVINE DEPT COMP & INFORMAT SCIIRVINECA 92717

ISBN: (纸本)0818674237

The model refinement task in system-level synthesis transforms a specification from a functional model to a chosen implementation model. In this paper, we categorize several commonly-used implementation models and then describe a set of refinement procedures to transform a specification to each of these implementation models. We also present a set of experimental results to compare the implementation models and to demonstrate how the proposed approach is used to explore different implementation styles.

关键词： hardware-software codesign

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