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1996 IEEE/acm international conference on Computer-Aided Design

作者： Shin, YS Choi, KY Seoul Natl Univ Seoul South Korea

ISBN: (纸本)0818675977

Latency tolerance is one of main problems of software synthesis in the design of hardware-software mixed systems. This paper presents a methodology for speeding up systems through latency tolerance which is obtained by decomposition of tasks and generation of an efficient scheduler. The task decomposition process focuses on the dependency analysis of system i/o operations. Scheduling of the decomposed tasks is performed in a mixed static and dynamic fashion. Experimental results show the significance of our approach.

关键词： Computer aided software engineering

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ASAP: an asynchronous array processor for hardware-software coprocessing and codesign

ASAP: an asynchronous array processor for hardware-software ...

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Proceedings of the 1996 2nd international conference on ASIC

作者： Gao, Bo Rees, David J. Univ of Newcastle upon Tyne Newcastle upon Tyne United Kingdom

Traditional field programmable gate arrays (FPGAs) originate and are used to prototype digital designs. Recently, there has been increasing interest in using FPGAs as attached systems for hardware-software coprocessing and codesign. However, existing FPGAs on the market all implement general purpose logic designs. They are not well defined for the coprocessing and codesign purpose. In this paper, an analysis and comparison of existing FPGA architectures against requirements from synthesis process on algorithm specifications is described. Based on this analysis, the design of a configurable ASynchronous Array Processor (ASAP) and the development of a data-driven multiple thread computation model for the processor are presented. The system's performance is data dependent and measured by average instead of worst cases in synchronous FPGAs. The ASAP easily out-performs other coprocessing systems as a frame buffer by embedding a fast forward difference polynomial evaluation algorithm.

关键词： Parallel processing systems

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6th international Workshop on Field-Programmable Logic and Applications, FPL 1996

6th International Workshop on Field-Programmable Logic and A...

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6th international Workshop on Field-Programmable Logic and Applications, FPL 1996

ISBN: (纸本)9783540617303

The proceedings contain 50 papers. The special focus in this conference is on High-level Design I, New software and hardware Development Tools. The topics include: Portable pipeline synthesis for FCCMs;a framework for developing parametrised FPGA libraries;co-evaluation environment for FPGA architecture and CAD system;an universal CLA adder generator for SRAM-based FPGAs;a data driven computer on a virtual hardware;custom computing machines vs. hardware/software codesign;reconfigurable and adaptive computing environment;computing 2-D DFTs using FPGAs;computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping;architectural synthesis and efficient circuit implementation for field programmable gate arrays;reconfigurable pipelined datapath;solving satisfiability problems on FPGAs;FPGA implementation of the block-matching algorithm for motion estimation in image coding;parallel CRC computation in FPGAs;coherent demodulation with FPGAs;the trianus system and its application to custom computing;flexible codesign target architecture for early prototyping of CMIST systems;a reconfigurable multiprocessor testbed;a slow motion engine for the analysis of FPGA-based prototypes;implementing reconfigurable datapaths in FPGAs for adaptive filter design;a fast constant coefficient multiplier for the XC6200;key issues for user acceptance of FPGA design tools;reconfigurable DSP demonstrators for the development of spacecraft payload processors;reconfigurable logic based fibre channel network card with sub 2 micro-second raw latency;an instruction-level custom-configurable processor;architectural synthesis techniques for dynamically reconfigurable logic and fast reconfigurable crossbar switching in FPGAs.

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A hardware/software codesign case study: design of a robot arm controller 96

A hardware/software codesign case study: design of a robot a...

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European Design and Test (ED&TC) conference

作者： M. Abid A. Changuel A. Jerraya Laboratoire TIMA System Level Synthesis Group Grenoble France

ISBN: (纸本)9780818674235

This paper deals with exploration of hardware-software design space. The hardware/software partitioning is illustrated using a real-time robot arm controller. Several architectural solutions are discussed with regard to their performance and cost. The goal is to select the best solution that satisfies the real-time constraints and minimizes the cost.

关键词： hardware Computer aided software engineering Robot control Costs Orbital robotics Real time systems Velocity control Programmable control Adaptive control Control system synthesis

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Rapid prototyping of reconfigurable coprocessors

Rapid prototyping of reconfigurable coprocessors

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international conference on Application Specific systems (ASAP), Architectures and Processors

作者： N. Narasimhan V. Srinivasan M. Vootukuru J. Walrath S. Govindarajan R. Vemuri Laboratory for Digital Design Environments Department of ECECS University of Cincinnati USA

We describe the process of hardware-software codesign of a JPEG-like still image compression system. The hardware components are targeted to execute on a reconfigurable hardware coprocessor which communicates with a host computer that executes all the software tasks. Central to our codesign methodology is the usage of software profiling, high-level estimation and synthesis tools. We describe the process of trade-off analysis and hardware task selection in detail. We present detailed experimental results gathered throughout the codesign process.

关键词： Prototypes Coprocessors hardware Field programmable gate arrays Image coding software prototyping Logic arrays Random access memory Read-write memory Process design

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hardware/software partitioning using integer programming 96

Hardware/software partitioning using integer programming

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European Design and Test (ED&TC) conference

作者： R. Niemann P. Marwedel Department of Computer Science XII University of Dortmund Dortmund Germany

ISBN: (纸本)9780818674235

One of the key problems in hardware/software codesign is hardware/software partitioning. This paper describes a new approach to hardware/software partitioning using integer programming (IP). The advantage of using IP is that optimal results are calculated respective to the chosen objective function. The partitioning approach works fully automatic and supports multi-processor systems, interfacing and hardware sharing. In contrast to other approaches where special estimators are used, we use compilation and synthesis tools for cost estimation. The increased time for calculating the cost metrics is compensated by an improved quality of the estimations compared to the results of estimators. Therefore, fewer iteration steps of partitioning will be needed. The paper shows that using integer programming to solve the hardware/software partitioning problem is feasible and leads to promising results.

关键词： hardware Linear programming Iterative algorithms Partitioning algorithms Cost function Embedded system Processor scheduling software algorithms Application software Digital signal processing

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ASAP: an asynchronous array processor for hardware-software coprocessing and codesign

ASAP: an asynchronous array processor for hardware-software ...

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international conference on ASIC

作者： Bo Gao D.J. Rees Department of E&E Engineering University of Newcastle Newcastle-upon-Tyne UK Department of Computer Science University of Edinburgh Edinburgh UK

关键词： Field programmable gate arrays Programmable logic arrays Prototypes Logic design Algorithm design and analysis Computer architecture Yarn Computational modeling system performance Polynomials

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Model refinement for hardware-software codesign 96

Model refinement for hardware-software codesign

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European Design and Test (ED&TC) conference

作者： Jie Gong D.D. Gajski S. Bakshi Semiconductor Systems Design Technolog Motorola Inc. Tempe AZ USA Department of Information and Computer Science University of California Irvine CA USA

ISBN: (纸本)9780818674235

The model refinement task in system-level synthesis transforms a specification from a functional model to a chosen implementation model. In this paper, we categorize several commonly-used implementation models and then describe a set of refinement procedures to transform a specification to each of these implementation models. We also present a set of experimental results to compare the implementation models and to demonstrate how the proposed approach is used to explore different implementation styles.

关键词： Application specific integrated circuits Computer science hardware

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Complexity management in system-level design

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JOURNAL OF VLSI SIGNAL PROCESSING systemS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 1996年第2期14卷 157-169页

作者： Kalavade, A Lee, EA Univ of California at Berkeley Berkeley United States

The system-level design problem spans a large design space. Typically, the designer needs to explore possible target architectures, experiment with different tools, and work with a range of constraints and optimization criteria. This design process is quite complex and involves considerable bookkeeping and management, in addition to sophisticated design tools. We believe that managing the design process is an important (although often neglected) part of system-level design. The contribution of this paper is in two parts. First, we present a framework for systematically managing the design process. Secondly, we illustrate how this framework can be used to manage a system-level design environment that consists of a suite of sophisticated hardware and software design tools. We begin by identifying some of the desirable features of system-level design methodology management. A candidate framework that manifests these features is presented. Complex design flows with iterative and conditional behavior can be specified within the framework. The framework also supports automated scheduling of tools in a well-defined design flow. It has been implemented as the DMM domain in Ptolemy. In the second part of the paper, we describe a case study that we have developed within this framework. The case study, called the Design Assistant, is a complete hardware-software codesign environment. It encapsulates various codesign tools for specification, partitioning, and synthesis;their interplay can be managed efficiently by the design methodology management framework.

关键词： Microprocessor chips

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software system for parsing signal processing tasks over multiple heterogeneous processors

Software system for parsing signal processing tasks over mul...

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conference on Advanced Signal Processing Algorithms

作者： WARSHAWSKY, EH JRS RES LABS INC ORANGECA 92665

ISBN: (纸本)0819419222

A design automation toolset of great applicability to the signal processing system design community is described herein, the JRS NetSyn product. NetSyn provides facilities for building and maintaining libraries of reusable hardware and software parts. The NetSyn methodology supports hardware/software codesign and tradeoffs and the distribution of software functions to processing elements in accordance with selected optimization objectives. NetSyn utilizes VHDL, Ada, and ANSI C standard languages and related tools. It facilities software reuse by porting application systems to alternative architectures. The paper presents some of the underlying concepts of NetSyn and then describes the functionality of the toolset in some detail.

关键词： DESIGN AUTOMATION synthesis SIMULATION hardware software codesign

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