This paper deals with the problems of system-level specification and partitioning in hardware/software co-design. It first discusses the implication of using VHDL as an implementation-independent specification languag...
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This paper deals with the problems of system-level specification and partitioning in hardware/software co-design. It first discusses the implication of using VHDL as an implementation-independent specification language. A message passing communication mechanism is proposed to relax the strict synchronization imposed by the simulation-based semantics of VHDL. A partitioning technique is then described which is used to partition the VHDL specification into a hardware part and a software part. The partitioning is carried out during the compilation process of VHDL into a design representation which identifies the hardware/software boundary, while capturing hardware and software in a uniform way to allow efficient co-synthesis of both parts. The VHDL compiler and the partitioning algorithm function as the front end of a hardware/software co-synthesis environment which is built on the design representation.
With our codesignsystem, POLIS, we have specified and implemented a real-life design: a shock absorber controller. Through this experiment, we have shown the possibility of using such a system to design complex appli...
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With our codesignsystem, POLIS, we have specified and implemented a real-life design: a shock absorber controller. Through this experiment, we have shown the possibility of using such a system to design complex applications and to speed up the design cycle dramatically. All aspects of the design process are closely scrutinized including high level language translation and automatic hardware and softwaresynthesis. We analyze different software implementation styles and draw some conclusions about our design process.
During the life cycle of a digital reactive real-time system implemented as a hardware-software board or chip, some of its components must be redesigned, either because a refocusing of the product market resulted in a...
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During the life cycle of a digital reactive real-time system implemented as a hardware-software board or chip, some of its components must be redesigned, either because a refocusing of the product market resulted in a specification change, or because bugs in the specification were found at a later stage of the design. We address the problem of automatically checking if a new version of a specification can utilize a hardware-software implementation of a previous version of the same specification by just changing the software portion of the design. The redesigning strategy we propose is divided into four phases. In the first phase, we check which parts of the specification were changed. In the second phase, we extract timing constraints from the previous hardware implementation that must be satisfied by the new software implementation. Then, we schedule and select the instructions in the software routine such that the timing constraints are observed. Finally, we check if the final implementation satisfies the specification rate constraints of the design. We present an example of a keyboard/mouse device, and we show that the hardware-softwaresynthesissystem can be made robust with respect to small changes in the specification.
Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded controllers. Target system of COSYMA is a core processor with application specific co-processors. The system speedup ...
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ISBN:
(纸本)9780897916905
Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded controllers. Target system of COSYMA is a core processor with application specific co-processors. The system speedup for standard programs compared to a single 33MHz RISC processor solution with fast, single cycle access RAM was typically less than 2 due to restrictions in high-level co-processor synthesis, and incorrectly estimated back end tool performance, such as hardwaresynthesis, compiler optimization and communication optimization. Meanwhile, a high-level synthesis tool for high-performance co-processors in co-synthesis has been developed. This paper explains the requirements and the main features of the high-level synthesis sytem and its integration into COSYMA. The results show a speedup of 10 in most cases. Compared to the speedup, the co-processor size is very small.
Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded controllers [ErHeBe93]. Target system of COSYMA is a core processor with application specific co-processors. The syst...
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Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded controllers [ErHeBe93]. Target system of COSYMA is a core processor with application specific co-processors. The system speedup for standard programs compared to a single 33MHz RISC processor solution with fast, single cycle access RAM was typically less than 2 due to restrictions in high-level co-processor synthesis, and incorrectly estimated back end tool performance, such as hardwaresynthesis, compiler optimization and communication optimization. Meanwhile, a high-level synthesis tool for high-performance co-processors in co-synthesis has been developed. This paper explains the requirements and the main features of the high-level synthesissystem and its integration into COSYMA. The results show a speedup of 10 in most cases. Compared to the speedup, the co-processor size is very small.
The aim of this paper is to define an approach, tailored for control-oriented applications, to manage system cospecification, high-level partitioning, hw/sw tradeoffs and cosynthesis. Our research effort focuses on fu...
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The aim of this paper is to define an approach, tailored for control-oriented applications, to manage system cospecification, high-level partitioning, hw/sw tradeoffs and cosynthesis. Our research effort focuses on fulfilling the goal of linking high-level specifications to efficient and cost-effective hw/sw implementations by investigating techniques such as synchronous cospecification styles, direct machine code generation as well as exploiting the capability of commercial VHDL synthesis tools.< >
A major element of codesign is the task of decomposing a design in order to target some of its components to hardware and some to software while maintaining the integrity of the execution model. We illustrate how a pr...
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ISBN:
(纸本)0818642300
A major element of codesign is the task of decomposing a design in order to target some of its components to hardware and some to software while maintaining the integrity of the execution model. We illustrate how a previously developed algebraic technique we call system factorization adapts to this notion of decomposition. As an example, we describe how the mechanization of system factorization was used in the formal derivation of an implementation of Hunt's FM9001 microprocessor description using the DDD design derivation system. This case study demonstrates the benefits to system-level design in combining an executable modeling language, its associated formal-reasoning systems, hardwaresynthesis tools, and a hardware development platform in an integrated prototyping environment.
A major element of codesign is the task of decomposing a design in order to target some of its components to hardware and some to software while maintaining the integrity of the execution model. We illustrate how a pr...
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A major element of codesign is the task of decomposing a design in order to target some of its components to hardware and some to software while maintaining the integrity of the execution model. We illustrate how a previously- developed algebraic technique which we call 'system factorization', adapts to this notion of decomposition. As an example, we describe how the mechanization of system factorization was used in the formal derivation of an implementation of Hunt's (1992) FM9001 microprocessor description using the DDD (digital design derivation) system. This case study demonstrates the benefits to system-level design in combinational-reasoning systems, hardwaresynthesis tools, and a hardware development platform in an integrated prototyping environment.< >
DProto is a computer-aided software engineering (CASE) system for rapidly prototyping concurrent applications. The environment supports codesign and analysis of high-level software and hardware architectures early in ...
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Microcontroller-based systems require the design of a hardware/software interface that enables software running on the microcontroller to control external devices. This interface consists of the sequential logic that ...
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ISBN:
(纸本)0818630108
Microcontroller-based systems require the design of a hardware/software interface that enables software running on the microcontroller to control external devices. This interface consists of the sequential logic that physically connects the devices to the microcontroller and the software drivers that allow code to access the device functions. This paper presents a method for automatically synthesizing this hardware/software interface using a recursive algorithm. Practical examples are used to demonstrate the utility of the method and results indicate that the synthesized circuit and driver code are comparable to that generated by human designers. This new tool will be used by higher-level synthesis tools to evaluate partitionings of a system between hardware and software components.
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