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FLASH: Fast Neural Architecture Search with hardware Optimization

acm TRANSACTIONS ON EMBEDDED COMPUTING systemS 2021年第5期20卷 63-63页

作者： Li, Guihong Mandal, Sumit K. Ogras, Umit Y. Marculescu, Radu Univ Texas Austin Austin TX 78712 USA Univ Wisconsin Madison WI USA

Neural architecture search (NAS) is a promising technique to design efficient and high-performance deep neural networks (DNNs). As the performance requirements of ML applications grow continuously, the hardware accelerators start playing a central role in DNN design. This trend makes NAS even more complicated and time-consuming for most real applications. This paper proposes FLASH, a very fast NAS methodology that co-optimizes the DNN accuracy and performance on a real hardware platform. As the main theoretical contribution, we first propose the NN-Degree, an analytical metric to quantify the topological characteristics of DNNs with skip connections (e.g., DenseNets, ResNets, Wide-ResNets, and MobileNets). The newly proposed NN-Degree allows us to do training-free NAS within one second and build an accuracy predictor by training as few as 25 samples out of a vast search space with more than 63 billion configurations. Second, by performing inference on the target hardware, we fine-tune and validate our analytical models to estimate the latency, area, and energy consumption of various DNN architectures while executing standard ML datasets. Third, we construct a hierarchical algorithm based on simplicial homology global optimization (SHGO) to optimize the model-architecture co-design process, while considering the area, latency, and energy consumption of the target hardware. We demonstrate that, compared to the state-of-the-art NAS approaches, our proposed hierarchical SHGO-based algorithm enables more than four orders of magnitude speedup (specifically, the execution time of the proposed algorithm is about 0.1 seconds). Finally, our experimental evaluations show that FLASH is easily transferable to different hardware architectures, thus enabling us to do NAS on a Raspberry Pi-3B processor in less than 3 seconds.

关键词： Neural networks network science hardware optimization neural architecture search model-architecture co-design resource-constrained devices

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Formal Verification of GCSE in the Scheduling of High-level synthesis: Work-in-Progress

Formal Verification of GCSE in the Scheduling of High-level ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jian Hu Yongyang Hu Long Yu Wentao Wang Haitao Yang Yun Kang Jie Cheng The Sixty-third Research Institute National University of Defense Technology NanJing China College of Computer Science and Technology National University of Defense Technology ChangSha China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/systemC) into a register-transfer level (RTL) implementation. However, an error may exist in the RTL implementation from the compiler in the high-level synthesis due to the complex and error prone compiling process. Global common subexpression elimination (GCSE) is a commonly used code motion technique in the scheduling of high-level synthesis. In this paper, we present an equivalence checking method to verify GCSE in the scheduling of high-level synthesis by enhancing the path equivalence criteria. The initial experimental results demonstrate our method can indeed verify the GCSE which has not been properly addressed in the past.

关键词： hardware Formal verification

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Aggressive Energy Reduction for Video Inference with software-only Strategies

Aggressive Energy Reduction for Video Inference with Softwar...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Goncalves, Larissa Rozales De Moura, Rafael Fao Carro, Luigi Univ Fed Rio Grande do Sul Porto Alegre RS Brazil

In the past years, several works have proposed custom hardware and software-based techniques for the acceleration of Convolutional Neural Networks (CNNs). Most of these works focus on saving computations by changing the used precision or modifying frame processing. To reach a more aggressive energy reduction, in this paper we propose software-only modifications to the CNNs inference process. Our approach exploits the inherent locality in videos by replacing entire frame computations with a movement prediction algorithm. Furthermore, when a frame must be processed, we avoid energy-demanding floating-point operations, and at the same time reduce memory accesses by employing look-up tables in place of the original convolutions. Using the proposed approach, one can reach significant energy gains of more than 25x for security cameras, and 12x for moving vehicles applications, with only small software modifications.

关键词： Convolutional Neural Networks frame predicton computation reuse

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Work-in-Progress: A Simulation Framework for Domain-Specific system-on-Chips

Work-in-Progress: A Simulation Framework for Domain-Specific...

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作者： Arda, Samet E. Anish, N. K. Goksoy, A. Alper Mack, Joshua Kumbhare, Nirmal Sartor, Anderson L. Akoglu, Ali Marculescu, Radu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Univ Arizona Elect & Comp Engn Tucson AZ USA Carnegie Mellon Univ Elect & Comp Engn Pittsburgh PA 15213 USA

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Work-in-Progress: EAST-DNN: Expediting Architectural SimulaTions Using Deep Neural Networks

Work-in-Progress: EAST-DNN: Expediting Architectural SimulaT...

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作者： Dutt, Arko Narasimman, Govind Jie, Lin Chandrasekhar, Vijay Ramaseshan Sabry, Mohamed M. NTU Singapore Singapore Singapore A STAR I2R Singapore Singapore Singapore

ISBN: (纸本)9781450369237

A rapid and accurate architectural simulator is a cornerstone for an efficient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 106 x speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2x better accuracy with at least 2.3x speedup compared to state-of-the-art.

关键词： Deep Neural Network hardware Accelerators

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Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage systems: Work-in-Progress

Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Liao, Jing Li, Zhengda Wang, Yi Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Peoples R China Shenzhen Univ Natl Engn Lab Big Data Syst Comp Technol Shenzhen Peoples R China

ISBN: (纸本)9781728191980

Current LSM-Tree-based blockchain storage system will assign the data from multiple system users to the same disk drive. This will lead to the inefficient usage of physical spaces in disk and cause extra compaction operations for LSM-Tree. This paper presents Meta Chain, a user-aware cross-layer space allocation strategy for blockchain storage systems. As a cross-layer design, Meta-Chain redesigns the organization of LSM-Tree and utilizes the rich functionalities provided by open-channel SSD. Experimental results show that Meta-Chain can effectively reduce write amplification and extend the lifetime of SSD in comparison with representative schemes.

关键词： Blockchain Storage system LSM-Tree Flash Memory Space Allocation Address Translation

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Accelerating Queries of MongoDB by an FPGA-based Storage Engine: Work-in-Progress

Accelerating Queries of MongoDB by an FPGA-based Storage Eng...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhan, Jinyu Wu, Junting Jiang, Wei Li, Ying Zhu, Jianping Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China Tencent Technol Shenzhen Co Ltd Shenzhen Peoples R China

ISBN: (纸本)9781728191980

In this paper, we propose a storage engine for MongoDB to accelerate the queries and reduce the memory usage. An FPGA-based query accelerator is deployed to speed up the queries while hot data is migrated from memory to SSD to reduce memory occupancy by our storage engine. Moreover, multiple query tasks of MongoDB are performed in parallel and query conditions are parameterized to support diversified queries. Based on TPC-H benchmark and Tencent data set, experimental results demonstrate that our storage engine can achieve higher query efficiency (saving up to 63.5% time overhead) and lower memory occupancy (reducing up to 73.4% memory usage) compared with traditional MongoDB.

关键词： Field programmable gate arrays (FPGA)

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An Energy-aware Spiking Neural Network hardware Mapping based on Particle Swarm Optimization and Genetic Algorithm

An Energy-aware Spiking Neural Network Hardware Mapping base...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Junxiu Liu Xingyue Huang Dong Jiang Yuling Luo School of Electronic Engineering Guangxi Normal University Guilin China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

Spiking Neuron Network (SNN) is a biological neural network model which shows great capability in the time series data processing and pattern recognition etc. according to the recent research. It has been implemented in hardware system with a good scalability, where the Networks-on-Chip (NoC) interconnection strategy is widely used for the data communications between the neurons. The mapping between a SNN and a NoC hardware system is one of the challenge for the development of the hardware SNNs. In this paper, a hybrid Particle Swarm Optimization (PSO) algorithm for hardware SNN mapping is proposed with the object of minimizing the energy consumption. Compared to the conventional PSO, it can search the mapping solutions through three directions which can speed up the finding. In the meantime, the Genetic Algorithm (GA) is combined to provide the mutation operation to avoid converging to the local optimum. A typical hardware SNN is used as the testbench and results show that an effective hardware SNN mapping is obtained with a low energy consumption, and local optimum is avoided compared to other approaches.

关键词： Energy consumption Neurons Time series analysis hardware Particle swarm optimization Biological neural networks Genetic algorithms

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Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage systems: Work-in-Progress

Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jing Liao Zhengda Li Yi Wang College of Computer Science and Software Engineering The National Engineering Laboratory for Big Data System Computing Technology Shenzhen University Shenzhen China

ISBN: (数字)9781728191980

ISBN: (纸本)9781728191997

Current LSM-Tree-based blockchain storage system will assign the data from multiple system users to the same disk drive. This will lead to the inefficient usage of physical spaces in disk and cause extra compaction operations for LSM - Tree. This paper presents Meta-Chain , a user-aware cross-layer space allocation strategy for blockchain storage systems. As a cross-layer design, Meta-Chain redesigns the organization of LSM - Tree and utilizes the rich functionalities provided by open-channel SSD. Experimental results show that Meta-Chain can effectively reduce write amplification and extend the lifetime of SSD in comparison with representative schemes.

关键词： Disk drives Blockchain Organizations Compaction Resource management

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Treble: Fast software Updates by Creating an Equilibrium in an Active software Ecosystem of Globally Distributed Stakeholders

Treble: Fast Software Updates by Creating an Equilibrium in ...

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作者： Yim, Keun Soo Malchev, Iliyan Hsieh, Andrew Burke, Dave Google 1600 Amphitheatre Pkwy Mountain View CA 94043 USA

This paper presents our experience with Treble, a two-year initiative to build the modular base in Android, a Java-based mobile platform running on the Linux kernel. Our Treble architecture splits the hardware independent core framework written in Java from the hardware dependent vendor implementations (e.g., user space device drivers, vendor native libraries, and kernel written in C/C++). Cross-layer communications between them are done via versioned, stable inter-process communication interfaces whose backward compatibility is tested by using two API compliance suites. Based on this architecture, we repackage the key Android software components that suffered from crucial post-launch security bugs as separate images. That not only enables separate ownerships but also independent updates of each image by interested ecosystem entities. We discuss our experience of delivering Treble architectural changes to silicon vendors and device makers using a yearly release model. Our experiments and industry rollouts support our hypothesis that giving more freedom to all ecosystem entities and creating an equilibrium are a transformation necessary to further scale the world largest open source ecosystem with over two billion active devices.

关键词： Open source ecosystem software architecture software update

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