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An Ultra-Low Energy Human Activity Recognition Accelerator for Wearable Health Applications

An Ultra-Low Energy Human Activity Recognition Accelerator f...

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Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Bhat, Ganapati Tuncel, Yigit An, Sizhe Lee, Hyung Gyu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Daegu Univ Sch Comp & Commun Engn Daegu 38453 South Korea

Human activity recognition (HAR) has recently received significant attention due to its wide range of applications in health and activity monitoring. The nature of these applications requires mobile or wearable devices with limited battery capacity. User surveys show that charging requirement is one of the leading reasons for abandoning these devices. Hence, practical solutions must offer ultra-low power capabilities that enable operation on harvested energy. To address this need, we present the first fully integrated custom hardware accelerator (HAR engine) that consumes 22.4 mu J per operation using a commercial 65 nm technology. We present a complete solution that integrates all steps of HAR, i.e., reading the raw sensor data, generating features, and activity classification using a deep neural network (DNN). It achieves 95% accuracy in recognizing 8 common human activities while providing three orders of magnitude higher energy efficiency compared to existing solutions.

关键词： Human activity recognition wearable electronics flexible hybrid electronics hardware accelerator low-power design health monitoring

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Work-in-Progress: Runtime Requirements Monitoring for State-based hardware

Work-in-Progress: Runtime Requirements Monitoring for State-...

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acm/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Seo, Minjun Lysecky, Roman Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

ISBN: (纸本)9781538655627

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： Runtime requirements verification hardware verification formal verification models non-intrusive monitoring

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FPGA HW/SW codesign Approach for Real-time Image Processing Using HLS

FPGA HW/SW Codesign Approach for Real-time Image Processing ...

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Communications, Control systems and Signal Processing (CCSSP), 2020 1st international conference on

作者： Mohamed Salah AZZAZ Abdelmadjd MAALI Redouane KAIBOU Ibrahim KAKOUCHE Mohamed SAAD Hocine HAMIL Ecole Militaire Polytechnique Laboratoire SEN Algiers Algeria Mouloud Mammeri University LAMPA Laboratory Tizi-Ouzou Algeria

ISBN: (数字)9781728158358

ISBN: (纸本)9781728158365

Real-time constraint is one of the most common challenges found in many critical embedded applications, namely image and video processing. However, software tools such as Matlab and general purpose microprocessor are not suitable for deals with such a problem. Recently, FPGA reconfigurable circuit with its HLS software tools is become a very promising technology to be widely used in many applications encompassing all aspects and requirements of embedded system. This paper presents the implementation of morphological image operation including dilation, erosion and linear filtering. The implementation method is based on hardware/software (HW/SW) codesign approach using High Level synthesis (HLS) tools, Xilinx Vivado 15.2 and SDK 15.2. Zedboard FPGA platform with Zynq device is used for this work in which is connected to a PC through an Ethernet link. Captured image by Webcam is transmitted to the FPGA for processing and will be then returned to the PC to be displayed on the IHM interface, in real-time. Experimental results demonstrate the feasibility of the proposed approach and it can be extended for other applications.

关键词： Field programmable gate arrays Tools IP networks Convolution hardware Real-time systems Program processors

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Deriving Equations from Sensor Data Using Dimensional Function synthesis

Deriving Equations from Sensor Data Using Dimensional Functi...

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作者： Wang, Youchao Willis, Sam Tsoutsouras, Vasileios Stanley-Marbell, Phillip Univ Cambridge 9 JJ Thomson Ave Cambridge CB3 0FA England

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data streams where the dimensions of the signals are known. The method comprises two phases: a compile-time synthesis phase and a subsequent calibration using sensor data. We implement dimensional function synthesis and use the implementation to demonstrate efficiently summarizing multi-modal sensor data for two physical systems using 90 laboratory experiments and 10 000 synthetic idealized measurements. We evaluate the performance of the compile-time phase of dimensional function synthesis as well as the calibration phase overhead, inference latency, and accuracy of the models our method generates. The results show that our technique can generate models in less than 300 ms on average across all the physical systems we evaluated. When calibrated with sensor data, our models outperform traditional regression and neural network models in inference accuracy in all the cases we evaluated. In addition, our models perform better in training latency (over 8660x improvement) and required arithmetic operations in inference (over 34x improvement). These significant gains are largely the result of exploiting information on the physics of signals that has hitherto been ignored.

关键词： Machine learning dimensional analysis sensor data fusion

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Work-in-Progress: Physics-Based software Analysis for Safety-Critical Embedded Applications

Work-in-Progress: Physics-Based Software Analysis for Safety...

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作者： Goettlich, Philipp Reuss, Hans-Christian ETAS GmbH Stuttgart Germany Univ Stuttgart Stuttgart Germany

ISBN: (纸本)9781450369244

Physics-based software systems are a new trend in automotive feature and control implementation. They are used for modern applications in the context of automated driving and ADAS. Implementing physical models on critical embedded targets (for example electronic control systems) causes many safety related challenges, as they are far more complex than ordinary control algorithms. The code needs to be secured appropriately. This paper proposes a new approach to include physical properties in the V&V (verification & validation) and testing process in order to analyze functional code behavior of physical systems on targets automatically. For this, physical properties are extracted from the physics-based models, compared with databases and defined as constraints in order to analyze discretizations and calculations of the code. The mass conservation law for example is very beneficial for evaluating different discretization methods of model code automatically. This way, an evaluation of the correct behavior is faster, more efficient and safety and development time of physics-based embedded application code is improved. Our approach proved to be useful in finding physics-related errors in physics-based embedded systems automatically. The generated physical constraints can be used for test data generation.

关键词： Physical properties

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Work-in-Progress: hardware Implementation of a Multi-Mode-Aware Mixed-Criticality Scheduler

Work-in-Progress: Hardware Implementation of a Multi-Mode-Aw...

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acm/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hounsinou, Sena Vasu, Aishwarya Ramaprasad, Harini Southern Illinois Univ Carbondale IL 62901 USA Univ N Carolina Charlotte NC USA

ISBN: (纸本)9781538655627

To minimize size, weight, power, and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

关键词： Task analysis hardware Real-time systems Monitoring Registers software Processor scheduling

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Polar: Function Code Aware Fuzz Testing of ICS Protocol

Polar: Function Code Aware Fuzz Testing of ICS Protocol

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作者： Luo, Zhengxiong Zuo, Feilong Jiang, Yu Gao, Jian Jiao, Xun Sun, Jiaguang Tsinghua Univ Sch Software BNRist KLISS Beijing Peoples R China Villanova Univ Dept Comp Sci & Engn Villanova PA 19085 USA

Industrial Control system (ICS) protocols are widely used to build communications among system components. Compared with common internet protocols, ICS protocols have more control over remote devices by carrying a specific field called "function code", which assigns what the receive end should do. Therefore, it is of vital importance to ensure their correctness. However, traditional vulnerability detection techniques such as fuzz testing are challenged by the increasing complexity of these diverse ICS protocols. In this paper, we present a function code aware fuzzing framework - Polar, which automatically extracts semantic information from the ICS protocol and utilizes this information to accelerate security vulnerability detection. Based on static analysis and dynamic taint analysis, Polar initiates the values of the function code field and identifies some vulnerable operations. Then, novel semantic aware mutation and selection strategies are designed to optimize the fuzzing procedure. For evaluation, we implement Polar on top of two popular fuzzers - AFL and AFLFast, and conduct experiments on several widely used ICS protocols such as Modbus, IEC104, and IEC 61850. Results show that, compared with AFL and AFLFast, Polar achieves the same code coverage and bug detection numbers at the speed of 1.5X-12X. It also gains increase with 0%-91% more paths within 24 hours. Furthermore, Polar has exposed 10 previously unknown vulnerabilities in those protocols, 6 of which have been assigned unique CVE identifiers in the US National Vulnerability Database.

关键词： Fuzz testing industrial control system protocol function code vulnerability detection

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ReSQM: Accelerating Database Operations Using ReRAM-Based Content Addressable Memory

ReSQM: Accelerating Database Operations Using ReRAM-Based Co...

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作者： Li, Huize Jin, Hai Zheng, Long Liao, Xiaofei National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

The huge amount of data enforces great pressure on the processing efficiency of database systems. By leveraging the in-situ computing ability of emerging nonvolatile memory, processing-in-memory (PIM) technology shows great potential in accelerating database operations against traditional architectures without data movement overheads. In this article, we introduce ReSQM, a novel ReCAM-based accelerator, which can dramatically reduce the response time of database systems. The key novelty of ReSQM is that some commonly used database queries that would be otherwise processed inefficiently in previous studies can be in-situ accomplished with massively high parallelism by exploiting the PIM-enabled ReCAM array. ReSQM supports some typical database queries (such as SELECTION, SORT, and JOIN) effectively based on the limited computational mode of the ReCAM array. ReSQM is also equipped with a series of hardware-algorithm co-designs to maximize efficiency. We present a new data mapping mechanism that allows enjoying in-situ in-memory computations for SELECTION operating upon intermediate results. We also develop a count-based ReCAM-specific algorithm to enable the in-memory sorting without any row swapping. The relational comparisons are integrated for accelerating inequality join by making a few modifications to the ReCAM cells with negligible hardware overhead. The experimental results show that ReSQM can improve the (energy) efficiency by $611\times $ ( $193\times $ ), $19\times $ ( $17\times $ ), $59\times $ ( $43\times $ ), and $307\times $ ( $181\times $ ) in comparison to a 10-core Intel Xeon E5-2630v4 processor for SELECTION, SORT, equi-join, and inequality join, respectively. In contrast to state-of-the-art CMOS-based CAM, GPU, FPGA, NDP, and PIM solutions, ReSQM can also offer $2.2\times 39\times $ speedups. © 1982-2012 IEEE.

关键词： Query languages

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High-Level synthesis of Approximate Designs under Real-Time Constraints

High-Level Synthesis of Approximate Designs under Real-Time ...

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作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

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Work-in-Progress: AMVP - A High Performance Virtual Platform using Parallel systemC for Multicore ARM Architectures

Work-in-Progress: AMVP - A High Performance Virtual Platform...

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acm/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Weinstock, Jan Henrik Bucs, Robert Lajos Walbroel, Florian Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9781538655627

This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the performance slowdown incurred when simulating multi-processor designs. AMVP is sufficiently detailed to support running and debugging unmodified SW images of popular benchmark applications and modern OS kernels like Linux.

关键词： Electronic system Level Parallel Discrete Event Simulation Parallel systemC Simulation

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