检索结果-内蒙古大学图书馆

acm/IEEE international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Wehbe, Taimour Mooney, Vincent J. Keezer, David C. Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781538655627

The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.

关键词： security in hardware hardware attacks and countermeasures malicious design modifications embedded systems security sensor networks hardware Trojans data integrity

来源：评论

学校读者我要写书评

暂无评论

SWARAM: Portable Energy and Cost Efficient Embedded system for Genomic Processing

SWARAM: Portable Energy and Cost Efficient Embedded System f...

引用

Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Mohanty, Ram Prasad Gamaarachchi, Hasindu Lambert, Andrew Parameswaran, Sri Univ New South Wales Canberra ACT 2612 Australia Univ New South Wales Sydney NSW 2052 Australia

Treatment of patients using high-quality precision medicine requires a thorough understanding of the genetic composition of a patient. Ideally, the identification of unique variations in an individual's genome is needed for specifying the necessary treatment. Variant calling workflow is a pipeline of tools, integrating state of the art software systems aimed at alignment, sorting and variant calling for the whole genome sequencing (WGS) data. This pipeline is utilized for identifying unique variations in an individual's genome (compared to a reference genome). Currently, such a workflow is implemented on high-performance computers (with additional GPUs or FPGAs) or in cloud computers. Such systems are large, have a high cost, and rely on the internet for genome data transfer which makes the system unusable in remote locations unequipped with internet connectivity. It further raises privacy concerns due to processing being carried out in a different facility. To overcome such limitations, in this paper, for the first time, we present a cost-efficient, offline, scalable, portable, and energy-efficient computing system named SWARAM for variant calling workflow processing. The system uses novel architecture and algorithms to match against partial reference genomes to exploit smaller memory sizes which are typically available in tiny processing systems. Extensive tests on a standard benchmark data-set (NA12878 Illumina platinum genome) confirm that the time consumed for the data transfer and completing variant calling workflow on SWARAM was competitive to that of a 32-core Intel Xeon server with similar accuracy, but costs less than a fifth, and consumes less than 40% of the energy of the server system. The original scripts and code we developed for executing the variant calling workflow on SWARAM are available in the associated Github repository https://***/Rammohanty/swaram.

关键词： Genome alignment variant calling genetic analysis embedded system ARM DNA analysis energy efficient system portable genome analysis

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: EAST-DNN: Expediting Architectural SimulaTions Using Deep Neural Networks

Work-in-Progress: EAST-DNN: Expediting Architectural SimulaT...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Arko Dutt Govind Narasimman Lin Jie Vijay Ramaseshan Chandrasekhar Mohamed M. Sabry NTU Singapore A*STAR I2R Singapore

A rapid and accurate architectural simulator is a cornerstone for an emcient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 10 6 × speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2× better accuracy with at least 2.3× speedup compared to state-of-the-art.

关键词： Radio frequency Neural networks Acceleration hardware Boosting Training Computational modeling

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Drama: A High Efficient Neural Network Accelerator on FPGA using Dynamic Reconfiguration

Work-in-Progress: Drama: A High Efficient Neural Network Acc...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Yang Yang Chao Wang Xuehai Zhou University of Science and Technology of China Suzhou China

In this paper, we propose a high efficient neural network accelerator on FPGA by using dynamic reconfiguration, named Drama. Firstly, we design a high-efficient hardware architecture and provide a hardware template that can generate optimal configuration for each layer. Then, to explore the key features of the neural network models, we employ a layer-clustering algorithm to classify different layers. After that, we transform CNN models into task sequences. To accomplish the execution of the sequence, the FPGA-based hardware is able to switch the accelerator with dynamic reconfiguration and offload the related tasks to the accelerator at runtime. Preliminary results on the FPGA platform demonstrate that Drama is able to improve the performance significantly due to the dynamic reconfiguration techniques.

关键词： Field programmable gate arrays hardware Neural networks Task analysis Parallel processing Bandwidth Runtime

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: A Simulation Framework for Domain-Specific system-on-Chips

Work-in-Progress: A Simulation Framework for Domain-Specific...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Samet E. Arda NK Anish A. Alper Goksoy Joshua Mack Nirmal Kumbhare Anderson L. Sartor Ali Akoglu Radu Marculescu Umit Y. Ogras School of Electrical Computer and Energy Engineering Arizona State University Tempe AZ USA Electrical and Computer Engineering The University of Arizona Tucson AZ USA Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Homogeneous general purpose processors provide flexibility to implement a variety of applications and facilitate programmability. In contrast, heterogeneous system-on-chips (SoCs) that combine general purpose and specialized processors offer great potential to achieve higher efficiency while maintaining programming flexibility. In particular, domain-specific SoCs (DSSoC), a class of heterogeneous architectures, tailor the architecture and processing elements (PE) to a specific domain. Hence, they can provide superior energy-efficiency compared to general purpose processors by exploiting the characteristics of target applications.

关键词： Task analysis Schedules Computer architecture Heuristic algorithms Dynamic scheduling hardware

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: A concept of a hardware design environment with the functional language Elixir

Work-in-Progress: A concept of a hardware design environment...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Hideki Takase Kentaro Matsui Yoshihiro Ueno Masakazu Mori Yuki Hisae Susumu Yamazaki JST PRESTO Japan Kyoto University Sakyo-ku Kyoto Japan Delight Systems Co. Ltd. Chuo-ku Fukuoka Japan Karabiner Technology Inc. Chuo-ku Fukuoka Japan The University of Kitakyushu Wakamatsu-ku Kitakushu Japan

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： hardware Field programmable gate arrays hardware design languages Distributed databases IP networks Parallel processing Pipelines

来源：评论

学校读者我要写书评

暂无评论

2015 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2015

2015 International Conference on Hardware/Software Codesign ...

引用

international conference on hardware/software codesign and system synthesis, CODES+ISSS 2015

ISBN: (纸本)9781467383219

The proceedings contain 24 papers. The topics discussed include: how to improve the space utilization of Dedup-based PCM storage devices?;a tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones;lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs;improved hard real-time scheduling of CSDF-modeled streaming applications;hardware synthesis from a recursive functional language;power-awareness and smart-resource management in embedded computing systems;an online wear state monitoring methodology for off-the-shelf embedded processors;big/little deep neural network for ultra low power inference;an approximate compressor for wearable biomedical healthcare monitoring systems;and fast parallel application and multiprocessor design space exploration from sequential code.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Dynamic data management for automotive Ecus with hybrid RAM-NVM Memory

Work-in-Progress: Dynamic data management for automotive Ecu...

引用

2018 acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2018

作者： Zhan, Jinyu Yang, Junhuan Jiang, Wei Li, Yixin School of Information Software Engineering University of Electronic Science Technology of China China

ISBN: (纸本)9781538655627

Non-Volatile Memory (NVM) can be utilized to improve performance of automotive electronic systems, but frequent writings on NVM will decrease its lifetime. In this paper, we propose a Vehicle Dynamic Data Management (VDDM) scheme, which can distinguish the hot or cold data generated by vehicle Electronic Control Units (ECUs) and sensors, and manage the data to reduce the writing operations on NVM of the hybrid main memory. Experimental results show that VDDM can significantly reduce writing operations and prolong lifetime of NVM compared with other approaches. © 2018 IEEE.

关键词： Random access storage

来源：评论

学校读者我要写书评

暂无评论

Type-Directed Program synthesis and Constraint Generation for Library Portability 28

Type-Directed Program Synthesis and Constraint Generation fo...

引用

28th international conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Collie, Bruce Ginsbach, Philip O'Boyle, Michael F. P. Univ Edinburgh Sch Informat Edinburgh Midlothian Scotland

ISBN: (纸本)9781728136134

Fast numerical libraries have been a cornerstone of scientific computing for decades, but this comes at a price. Programs may be tied to vendor specific software ecosystems resulting in polluted, non-portable code. As we enter an era of heterogeneous computing, there is an explosion in the number of accelerator libraries required to harness specialized hardware. We need a system that allows developers to exploit ever-changing accelerator libraries, without over-specializing their code. As we cannot know the behavior of future libraries ahead of time, this paper develops a scheme that assists developers in matching their code to new libraries, without requiring the source code for these libraries. Furthermore, it can recover equivalent code from programs that use existing libraries and automatically port them to new interfaces. It first uses program synthesis to determine the meaning of a library, then maps the synthesized description into generalized constraints which are used to search the program for replacement opportunities to present to the developer. We applied this approach to existing large applications from the scientific computing and deep learning domains. Using our approach, we show speedups ranging from 1.1x to over 10x on end to end performance when using accelerator libraries.

关键词： program synthesis code rejuvenation constraint programming compilers

来源：评论

学校读者我要写书评

暂无评论

Coherent Extension, Composition, and Merging Operators in Contract Models for system Design

引用

acm TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 86-86页

作者： Passerone, Roberto Romeo, Inigo Incer Sangiovanni-Vincentelli, Alberto L. Univ Trento Dipartimento Ingn & Sci Informaz Via Sommar 9 I-38123 Trento Italy Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

Contract models have been proposed to promote and facilitate reuse and distributed development. In this paper, we cast contract models into a coherent formalism used to derive general results about the properties of their operators. We study several extensions of the basic model, including the distinction between weak and strong assumptions and maximality of the specification. We then analyze the disjunction and conjunction operators, and show how they can be broken up into a sequence of simpler operations. This leads to the definition of a new contract viewpoint merging operator, which better captures the design intent in contrast to the more traditional conjunction. The adjoint operation, which we call separation, can be used to repartition the specification into different viewpoints. We show the symmetries of these operations with respect to composition and quotient.

关键词： Interface contract merging conformance separation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：