检索结果-内蒙古大学图书馆

Proceedings of the international conference on hardware/software codesign and system synthesis Companion

作者： Arko Dutt Govind Narasimman Lin Jie Vijay Ramaseshan Chandrasekhar Mohamed M. Sabry NTU Singapore ASTAR IR Singapore

ISBN: (纸本)9781450369237

A rapid and accurate architectural simulator is a cornerstone for an efficient design-space exploration of computing systems. In this paper, we introduce EAST-DNN, a feed-forward deep neural network, to accelerate architectural simulations. EAST-DNN achieves > 106X speedup with an average prediction error of 4.3% over the baseline simulator. It also achieves an average of 2X better accuracy with at least 2.3X speedup compared to state-of-the-art.

关键词： deep neural network hardware accelerators

来源：评论

学校读者我要写书评

暂无评论

Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS

引用

acm TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 76-76页

作者： Dugo, Alexy Torres Aurora Lefoul, Jean-Baptiste De Magalhaes, Felipe Gohring Assal, Dahman Nicolescu, Gabriela Ecole Polytech Montreal 2900 Boul Edouard Montpetit Montreal PQ Canada Mannarino Syst & Software Inc Montreal PQ Canada

Avionic software is the subject of stringent real time, determinism and safety constraints. software designers face several challenges, one of them being the interferences that appear in common situations, such as resource sharing. The interferences introduce non-determinism and delays in execution time. One of the main interference prone resources are cache memories. In single-core processors, caches comprise multiple private levels. This breaks the isolation principle imposed by avionic standards, such as the ARINC-653. This standard defines partitioned architectures where one partition should never directly interfere with another one. In cache-based architectures, one partition can modify the cache content of another partition. In this paper, we propose a method based on cache locking to reduce the non-determinism and the contention on lower level memories while improving the time performances.

关键词： Critical systems ARINC-653 interference cache locking aerospace

来源：评论

学校读者我要写书评

暂无评论

ICCAD-2005 international conference on Computer Aided Design (IEEE Cat. No. 05CH37700) 05

ICCAD-2005 International Conference on Computer Aided Design...

引用

Proceedings of the 2005 IEEE/acm international conference on Computer-aided design

ISBN: (纸本)9780780392540

The following topics are dealt with: memory and arithmetic optimization; design manufacturing interaction; circuit layout; digital analog and RF test; design for manufacturing; logic synthesis; double-gated devices; network routing and application specific NoC architectures; memory driven codes; arithmetic constructs; buffers and voltage islands; sequential circuit optimization; nanoelectronics; dynamic voltage scaling; biochips and DNA-based nanofabrication; circuit simulation; analog circuit design; power aware system architecture; software optimization; cellular array architectures; variability aware clocking; oscillator analysis; power noise and thermal issues; nanocomputing; extraction and modeling for interconnect structures; system-level variability modeling; high-level synthesis; model order reduction; statistical timing analysis; formal verification; hardware and software design of sensors; formal equivalence checking and system on chip.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Treble: Fast software Updates by Creating an Equilibrium in an Active software Ecosystem of Globally Distributed Stakeholders

引用

acm TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 104-104页

作者： Yim, Keun Soo Malchev, Iliyan Hsieh, Andrew Burke, Dave Google 1600 Amphitheatre Pkwy Mountain View CA 94043 USA

This paper presents our experience with Treble, a two-year initiative to build the modular base in Android, a Java-based mobile platform running on the Linux kernel. Our Treble architecture splits the hardware independent core framework written in Java from the hardware dependent vendor implementations (e.g., user space device drivers, vendor native libraries, and kernel written in C/C++). Cross-layer communications between them are done via versioned, stable inter-process communication interfaces whose backward compatibility is tested by using two API compliance suites. Based on this architecture, we repackage the key Android software components that suffered from crucial post-launch security bugs as separate images. That not only enables separate ownerships but also independent updates of each image by interested ecosystem entities. We discuss our experience of delivering Treble architectural changes to silicon vendors and device makers using a yearly release model. Our experiments and industry rollouts support our hypothesis that giving more freedom to all ecosystem entities and creating an equilibrium are a transformation necessary to further scale the world largest open source ecosystem with over two billion active devices.

关键词： Open source ecosystem software architecture software update

来源：评论

学校读者我要写书评

暂无评论

Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization

引用

acm TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 54-54页

作者： Sridhar, Aditya Ibrahim, Mohamed Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn 130 Hudson Hall Durham NC 27708 USA

Flow-based microfluidic biochips can be used to perform bioassays by manipulating a large number of on-chip valves. These biochips are increasingly used today for biomolecular recognition, single-cell screening, and point-of-care disease diagnostics, and design-automation solutions for flow-based microfluidics enable the mapping and optimization of bimolecular protocols and software-based valve control. However, a key problem that has not received adequate attention is chip-to-world interfacing, which requires the use of off-chip control equipment to provide control signals for the on-chip valves. This problem is exacerbated by the increase in the number of valves as chips get more complex. To address the interfacing problem, we present an efficient pin-count minimization (synthesis) problem, referred to as Synterface, which uses on-chip microfluidic logic gates and optimization based on concepts from linear algebra. We present results to show that Synterface significantly reduces pin-count and simplifies the external interface for flow-based microfluidics.

关键词： Microfluidic biochips chip-to-world interfacing synthesis logic gates

来源：评论

学校读者我要写书评

暂无评论

A concept of a hardware design environment with the functional language elixir: work-in-progress 19

A concept of a hardware design environment with the function...

引用

Proceedings of the international conference on hardware/software codesign and system synthesis Companion

作者： Hideki Takase Kentaro Matsui Yoshihiro Ueno Masakazu Mori Yuki Hisae Susumu Yamazaki Kyoto University Sakyo-ku Kyoto Japan Delight Systems Co. Ltd. Chuo-ku Fukuoka Japan Karabiner Technology Inc. Chuo-ku Fukuoka Japan The University of Kitakyushu Wakamatsu-ku Kitakushu Japan

ISBN: (纸本)9781450369237

The functional language Elixir is designed to be effective for the application. One of the most considerable feature of Elixir is that it is easy to realize the parallel processing with the standard library, such as Flow. In this paper, we study a design environment for hardware circuits using Elixir as a design language. We propose a synthesize flow for data flow hardware on the FPGA from the native Elixir code. Our method synthesizes functional equivalence circuits from the description of Enum and Flow in Elixir, which are libraries for direct manipulation and parallel processing of data collection in Elixir. Data flow is implemented base on the pipeline operator |> which connects the processing relation of the function by the data processing order. To realize a hardware design environment by Elixir, this paper shares current status of our implementation.

关键词： functional language elixir high-level synthesis

来源：评论

学校读者我要写书评

暂无评论

A simulation framework for domain-specific system-on-chips: work-in-progress 19

A simulation framework for domain-specific system-on-chips: ...

引用

Proceedings of the international conference on hardware/software codesign and system synthesis Companion

作者： Samet E. Arda Anish NK A. Alper Goksoy Joshua Mack Nirmal Kumbhare Anderson L. Sartor Ali Akoglu Radu Marculescu Umit Y. Ogras Arizona State University The University of Arizona Carnegie Mellon University

ISBN: (纸本)9781450369237

Homogeneous general purpose processors provide flexibility to implement a variety of applications and facilitate programmability. In contrast, heterogeneous system-on-chips (SoCs) that combine general purpose and specialized processors offer great potential to achieve higher efficiency while maintaining programming flexibility. In particular, domain-specific SoCs (DSSoC), a class of heterogeneous architectures, tailor the architecture and processing elements (PE) to a specific domain. Hence, they can provide superior energy-efficiency compared to general purpose processors by exploiting the characteristics of target applications.

关键词：

来源：评论

学校读者我要写书评

暂无评论

An Ultra-Low Energy Human Activity Recognition Accelerator for Wearable Health Applications

引用

acm TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 49-49页

作者： Bhat, Ganapati Tuncel, Yigit An, Sizhe Lee, Hyung Gyu Ogras, Umit Y. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Daegu Univ Sch Comp & Commun Engn Daegu 38453 South Korea

Human activity recognition (HAR) has recently received significant attention due to its wide range of applications in health and activity monitoring. The nature of these applications requires mobile or wearable devices with limited battery capacity. User surveys show that charging requirement is one of the leading reasons for abandoning these devices. Hence, practical solutions must offer ultra-low power capabilities that enable operation on harvested energy. To address this need, we present the first fully integrated custom hardware accelerator (HAR engine) that consumes 22.4 mu J per operation using a commercial 65 nm technology. We present a complete solution that integrates all steps of HAR, i.e., reading the raw sensor data, generating features, and activity classification using a deep neural network (DNN). It achieves 95% accuracy in recognizing 8 common human activities while providing three orders of magnitude higher energy efficiency compared to existing solutions.

关键词： Human activity recognition wearable electronics flexible hybrid electronics hardware accelerator low-power design health monitoring

来源：评论

学校读者我要写书评

暂无评论

High-Level synthesis of Approximate Designs under Real-Time Constraints

引用

acm TRANSACTIONS ON EMBEDDED COMPUTING systemS 2019年第5期18卷 59-59页

作者： Leipnitz, Marcos T. Nazar, Gabriel L. Univ Fed Rio Grande do Sul Informat Inst Av Bento Goncalves 9500 BR-91501970 Porto Alegre RS Brazil

The adoption of High-Level synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

关键词： High-level synthesis approximate computing worst-case execution time design space exploration

来源：评论

学校读者我要写书评

暂无评论

Run-time Requirement Enforcement for Loop Programs on Processor Arrays 18

Run-time Requirement Enforcement for Loop Programs on Proces...

引用

16th acm/IEEE international conference on Formal Methods and Models for system Design (MEMOCODE)

作者： Witterauf, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9781538661956

Loop bounds are often unknown until run time, making it difficult to analyze non-functional properties such as latency at compile-time. Similarly, static allocations of processing resources to loop computations might be too conservative with respect to given performance requirements, or not optimal with respect to the energy consumption. To still satisfy requirements when accelerating loop nests under this uncertainty of loop bounds, we formalize and propose an approach to run-time requirement enforcement: at run time, select a mapping among a set of candidates that satisfies a given set of requirements while optimizing secondary objectives. Because the candidate search space of suitable mappings might be prohibitively large to evaluate at run time, we further introduce two approaches to reduce its cardinality: 1) architecture-specific reduction by solving for parts of the mapping from the requirements, and 2) design-time reduction by finding a k-subset of mappings that maximizes the number of loop bounds where the requirements are satisfied. We implemented our proposed run-time requirement enforcement techniques for a representative class of programmable processor array architecture called tightly coupled processor arrays (TCPAs) and demonstrate their effectiveness with a case study. The case study shows the effectiveness of our approach: We can satisfy given latency requirements while easily saving up to 10% in energy.

关键词： embedded systems Linux multiprocessing systems parallel processing power aware computing program compilers program control structures reconfigurable architectures power aware computing program control structures Runtime Loops compilers Multiprocessing systems Reconfigurable architectures Contraceptive Coil Linux PARALLEL PROCESSING (COMPUTERS) Embedded systems MAPPING(MATHEMATICAL) ARRAY PROCESSORS enforcement

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：