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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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Work-in-Progress: A Fast Online Sequential Learning Accelerator for IoT Network Intrusion Detection 12

Work-in-Progress: A Fast Online Sequential Learning Accelera...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Huang, Hantao Khalid, Rai Suleman Liu, Wenye Yu, Hao Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore

ISBN: (纸本)9781450351850

Deployment of IoT devices for smart buildings and homes will offer a high level of comfortability with increased energy efficiency;but can also introduce potential cyber-attacks such as network intrusions via linked IoT devices. Due to the low-power and low-latency requirement to secure IoT network, traditional software based security system is not applicable. Instead, an embedded hardware-accelerator based data analytics is more preferred for network intrusion detection. In this paper, we propose an online sequential machine learning hardware accelerator to perform real-time network intrusion detection. A single hidden layer feedforward neural network based learning algorithm is developed with a least-squares solver realized on hardware. Experimental results on a single FPGA achieve a bandwidth of 409.6 Gbps with fast yet low-power network intrusion detection based on a number of benchmarks.

关键词： Intrusion detection hardware Training Field programmable gate arrays Benchmark testing Telecommunication traffic Computer architecture

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Work-in-Progress: A Unified Framework for Throughput Analysis of Synchronous Data Flow Graphs under Memory Constraints 12

Work-in-Progress: A Unified Framework for Throughput Analysi...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhu, Xue-Yang Chinese Acad Sci Inst Software State Key Lab Comp Sci Beijing 100190 Peoples R China

ISBN: (纸本)9781450351850

Streaming applications are often modeled with Synchronous data flow graphs (SDFGs). A proper analysis of the models is helpful to predict the performance of a system. In this paper, we focus on the throughput analysis of memory-constrained SDFGs (MC SDFGs), which needs to choose a memory abstraction that decides when the space of consumed data is released and when the required space is claimed. Different memory abstractions may lead to different achievable throughputs. The existing techniques, however, consider only a certain abstraction. If a model is implemented according to other abstractions, the analysis result may not truly evaluate the performance of the system. In this paper, we present a unified framework for throughput analysis of MC SDFGs for difference abstractions, aiming to provide evaluations matching up to the corresponding implementations.

关键词： Throughput Memory management Computational modeling Analytical models Electromagnetic compatibility Data models Flow graphs

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Special Session Paper: Exploiting Quality-Energy Tradeoffs with Arbitrary Quantization

Special Session Paper: Exploiting Quality-Energy Tradeoffs w...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Moreau, Thierry Augusto, Felipe Howe, Patrick Alaghi, Armin Ceze, Luis Univ Washington Seattle WA 98195 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781450351850

Approximate computing aims to expose and exploit quality vs. efficiency tradeoffs to enable ever-more demanding applications on energy-constrained devices such as smartphones, or IoT devices. This paper makes the case for arbitrary quantization as a compelling approximation technique that exposes quality vs. energy tradeoffs and provides practical error guarantees. We present QAPPA (Quality Autotuner for Precision Programmable Accelerators), an autotuning framework for C/C++ programs that automatically minimizes the precision of each arithmetic and memory operation to meet user defined application level quality guarantees. QAPPA integrates energy models of precision scaling mechanisms to produce bandwidth and energy savings estimates for precision scalable accelerator designs. We show that QAPPA can exploit precision scaling mechanisms to meet arbitrary user-provided quality targets on the PERFECT benchmark suite to achieve significant energy savings and memory bandwidth reduction.

关键词： Quantization (signal) Bandwidth Benchmark testing hardware Signal to noise ratio Adders Kernel

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Work-in-Progress: Communication Optimization for Thermal Reliable Many-core systems 12

Work-in-Progress: Communication Optimization for Thermal Rel...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Liu, Weichen Yang, Lei Jiang, Weiwen Guan, Nan Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Chongqing Univ Coll Comp Sci Chongqing Peoples R China Hong Kong Polytech Univ Dept Comp Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781450351850

system-level thermal management techniques normally map applications on non-adjacent cores to guarantee the safe temperature in many-core systems, while the communication efficiency will be oppositely affected by long-distance data transmission over conventional Network-on-Chips (NoC). SMART NoC has enabled single-cycle multi-hop bypass channels between distant cores, which can significantly reduce inter-processor communication latency. However, communication efficiency of SMART will be significantly diminished by express bypass break due to communication conflict. In order to achieve communication optimization with guaranteed system thermal reliability, we propose a dynamic re-configuration method for logical interconnection topology through task mapping on top of SMART NoC. Active cores are physically decentralized on chip for better heat dissipation, while communication overhead can be reduced by minimized communication conflict and maximized bypass routing. Applicability and effectiveness of the proposed technique can be improved with significant achievements in reducing communication overhead and improving application performance, compared with state-of-the-art techniques.

关键词： Reliability Silicon Schedules Topology Optimization system-on-chip

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Runtime requirements monitoring for state-based hardware: work-in-progress 18

Runtime requirements monitoring for state-based hardware: wo...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Minjun Seo Roman Lysecky University of Arizona

ISBN: (纸本)9781538655627

This paper presents a requirements-driven methodology enabling efficient runtime monitoring of hardware in embedded systems. We present a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph (HRMG) that can be efficiently used at runtime to verify correctness.

关键词： runtime requirements verification formal verification models hardware verification non-intrusive monitoring

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hardware implementation of a multi-mode-aware mixed-criticality scheduler: work-in-progress 18

Hardware implementation of a multi-mode-aware mixed-critical...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Sena Hounsinou Aishwarya Vasu Harini Ramaprasad Southern Illinois University University of North Carolina

ISBN: (纸本)9781538655627

To minimize size, weight, power, and cost, the industry aims at consolidating different criticality applications on the same hardware platform. In such a mixed-criticality environment, it is challenging to contain the overhead due to potential mode changes under overload conditions. Traditional scheduler implementation at the software level introduces additional overheads due to timer interrupt processing and context switching. To minimize overall software overhead and to improve timing predictability, in this paper, we propose an implementation of the mixed-criticality scheduler in the hardware that is capable of detecting task-overruns and making mode transitions seamlessly.

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Template based synthesis for high performance computing 25

Template based synthesis for high performance computing

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25th IFIP/IEEE international conference on Very Large Scale Integration (VLSI-SoC)

作者： Fujita, Masahiro Kimura, Yusuke Wang, Qinhao Univ Tokyo Tokyo Japan

ISBN: (纸本)9781538628805

Although FPGA based implementation of software can give us not only higher performance but also energy efficient computing, efficient implementation algorithms as hardware and as software can be significantly different. Typical high-level synthesis methods may not concentrate on this issue, as they are targeting general hardware designs. In this paper performance directed synthesis targeting throughput based computations rather than traditional high-level synthesis techniques is proposed based on "template based" approaches. With templates, given data flow graphs are automatically converted into the ones for high performance with FPGA implementation by using SAT-based automatic refinement methods. Several experimental case studies with the proposed synthesis methods are presented in order to demonstrate the usefulness of the proposed approach.

关键词： hardware Field programmable gate arrays Tools Pipeline processing High performance computing software Libraries

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AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress 18

AMVP - a high performance virtual platform using parallel sy...

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Proceedings of the international conference on hardware/software codesign and system synthesis

作者： Jan Henrik Weinstock Róbert Lajos Bücs Florian Walbroel Rainer Leupers Gerd Ascheid RWTH Aachen University

ISBN: (纸本)9781538655627

This paper presents AMVP - a systemC based simulator for ARM multicore platforms designed as a tool for early SW development during platform bring-up. It uses a parallel systemC simulation approach to counter the performance slowdown incurred when simulating multi-processor designs. AMVP is sufficiently detailed to support running and debugging unmodified SW images of popular benchmark applications and modern OS kernels like Linux.

关键词： parallel systemC simulation parallel discrete event simulation electronic system level

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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

2014 International Conference on Hardware/Software Codesign ...

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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

ISBN: (纸本)9781450330510

The proceedings contain 35 papers. The topics discussed include: HEFT: a hybrid system-level framework for enabling energy-efficient fault-tolerance in NoC based MPSoCs;an efficient technique for computing importance measures in automatic design of dependable embedded systems;towards scalable symbolic routing for multi-objective networked embedded system design and optimization;hardware/software co-design for a wireless sensor network platform;a PCM translation layer for integrated memory and storage management;leveraging microarchitectural side channel information to efficiently enhance program control flow integrity;saving energy without defying deadlines on mobile GPU-based heterogeneous systems;prediction and control of bursty cloud workloads: a fractal framework;TSP: thermal safe power - efficient power budgeting for many-core systems in dark silicon;and flattening-based mapping of imperfect loop nests for CGRA.

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A Streaming Clustering Approach Using a Heterogeneous system for Big Data Analysis 17

A Streaming Clustering Approach Using a Heterogeneous System...

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IEEE/acm 36th international conference on Computer-Aided Design (ICCAD)

作者： Lee, Dajung Althoff, Alric Richmond, Dustin Kastner, Ryan Univ Calif San Diego Dept Elect & Comp Engn La Jolla CA 92093 USA Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

ISBN: (纸本)9781538630938

Data clustering is a fundamental challenge in data analytics. It is the main task in exploratory data mining and a core technique in machine learning. As the volume, variety, velocity, and variability of data grows, we need more efficient data analysis methods that can scale towards increasingly large and high dimensional data sets. We develop a streaming clustering algorithm that is highly amenable to hardware acceleration. Our algorithm eliminates the need to store the data objects, which removes limits on the size of the data that we can analyze. Our algorithm is highly parameterizable, which allows it to fit to the characteristics of the data set, and scale towards the available hardware resources. Our streaming hardware core can handle more than 40 Msamples/s when processing 3-dimensional streaming data and up to 1.78 Msamples/s for 70-dimensional data. To validate the accuracy and performance of our algorithms we compare it with several common clustering techniques on several different applications. The experimental result shows that it outperforms other prior hardware accelerated clustering systems.

关键词： Online clustering streaming architecture hardware-software codesign FPGA hardware acceleration vector quantization

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