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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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FPGA-Accelerated for Constrained High Dispersal Network 15

FPGA-Accelerated for Constrained High Dispersal Network

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15th IEEE international Symposium on Parallel and Distributed Processing with Applications (ISPA) / 16th IEEE international conference on Ubiquitous Computing and Communications (IUCC)

作者： Chen, Yanliang Zhu, Minghua Xiao, Bo Meng, Dan East China Normal Univ MOE Res Ctr Software Hardware Codesign Engn & App Shanghai Peoples R China

ISBN: (纸本)9781538637906

In recent years, the Deep Neural Network (DNN) has been successfully used in image classification. Most of existing DNN often need to learn a very large set of parameters, which require a huge amount of computational resources and time to train these model parameters using the gradient descent and back-propagation procedure. To solve this issue, the PCANet has been developed for high efficient design and training of the DNN. Compared with traditional DNN, PCANet has simpler structure and better performance, which makes it attractive for hardware design. To overcome the limitations of PCANet and significantly improve its performance, we have proposed a novel model named Constrained High Dispersal Network (CHDNet) which is a variant of PCANet. In this paper, we implement the CHDNet on the Xilinx ZYNQ FPGA to ensure the instantaneity of the system with lower power than personal computer needed by taking advantage of the algorithmic parallelism and ZYNQ architecture. Our experimental results over two major datasets, the MNIST dataset for handwritten digits recognition, and the Extended Yale B dataset for face recognition, demonstrate that our model of implementation on FPGA is more than 15x faster than software implementation on PC (Intel i7-4720HQ, 2.6GHz).

关键词： Image classification Deep neural network FPGA High-level synthesis

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MEMOCODE 2017 - 15th acm-IEEE international conference on Formal Methods and Models for system Design

MEMOCODE 2017 - 15th ACM-IEEE International Conference on Fo...

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15th acm-IEEE international conference on Formal Methods and Models for system Design, MEMOCODE 2017

ISBN: (纸本)9781450350938

The proceedings contain 23 papers. The topics discussed include: the quest for average response time;stochastic contracts for cyber-physical system design under probabilistic requirements;on improving rare event simulation for probabilistic safety analysis;quantifying the information leak in cache attacks via symbolic execution;efficient realization of logical execution times in legacy embedded software;model-based availability analysis for automated production systems: a case study;model-based, mutation-driven test case generation via heuristic-guided branching search;automatic evaluation of complex design decisions in component-based software architectures;more than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models;property templates for checking source code security;formal verification and control synthesis of complex dynamic systems: model-based and data-driven methods;extraction of missing formal assumptions in under-constrained designs;hyperproperties of real-valued signals;using the Coq theorem prover to verify complex data structure invariants;a core calculus for secure hardware: its formal semantics and proof system;releasing VDM proof obligations with SMT solvers;and simulation of cyber-physical systems using IEC61499.

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Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress 17

Heterogeneous redundancy to address performance and cost in ...

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Proceedings of the Twelfth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： M. Naghashi S. H. Mozafari S. Hessabi Sharif University of Technology Tehran Iran McGill University Montreal Canada

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their specification in the first place: yie... 详细信息

ISBN: (纸本)9781450351850

关键词： system-level design redundancy manufacturability

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Implementing geo-blocking and spoofing protection in multi-domain software defined interconnects 1

Implementing geo-blocking and spoofing protection in multi-d...

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1st international Workshop on Security and Dependability of Multi-Domain Infrastructures, XDOM0 2017

作者： Kumary, Himal Mercian, Anu Banerjee, Sujata Russell, Craig Sivaramany, Vijay UNSW Australia Hewlett-Packard Enterprise United States VMware United States CSIRO Data 61 Australia

ISBN: (纸本)9781450349376

Motivated by recent attacks like the Australian census website meltdown in 2016, this paper proposes a system for high-level specification and synthesis of intents for Geo- Blocking and IP Spoofing protection at a software Defined Interconnect. In contrast to todays methods that use expensive custom hardware and/or manual configuration, our solution allows the operator to specify high-level intents, which are automatically compiled to flow-level rules and pushed into the interconnect fabric. We define a grammar for specifying the security policies, and a compiler for converting these to connectivity rules. We prototype our system on the open-source ONOS Controller platform, demonstrate its functionality in a multi-domain SDN fabric interconnecting legacy border routers, and evaluate its performance and scalability in blocking DDoS attacks. © 2017 acm.

关键词： software defined networking

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Towards the application of flask security architecture to SoC design: work-in-progress 17

Towards the application of flask security architecture to So...

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Proceedings of the Twelfth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Festus Hategekimana Christophe Bobda University of Arkansas

ISBN: (纸本)9781450351850

In this work, we explore a security reference monitor (RM) design which borrows from the Flask security architecture. Our RM design goal is to achieve complete mediation by checking and verifying the authority and the authenticity of every access to every system object in systems-on-chip (SoCs). Access decisions are administered by a security logic "server" implemented as an extension of the peripheral bus. Initial results show a minimal increase in resource overhead and no significant impact on the performance.

关键词： secure execution trojan hardware sandbox field programmable gate arrays (FPGAs) component authentication process systems-on-chip (SoC)

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Edge-TM: Exploiting transactional memory for error tolerance and energy efficiency

Edge-TM: Exploiting transactional memory for error tolerance...

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acm Transactions on Embedded Computing systems

作者： Papagiannopoulou, Dimitra Marongiu, Andrea Moreshet, Tali Herlihy, Maurice Bahar, R. Iris Department of Electrical and Computer Engineering University of Massachusetts Lowell LowellMA01854 United States Department of Information Technology and Electrical Engineering ETH Zurich Zurich8092 Switzerland College of Engineering Boston University BostonMA02215 United States Department of Computer Science Brown University ProvidenceRI02912 United States School of Engineering Brown University ProvidenceRI02912 United States

Scaling of semiconductor devices has enabled higher levels of integration and performance improvements at the price of making devices more susceptible to the effects of static and dynamic variability. Adding safety margins (guardbands) on the operating frequency or supply voltage prevents timing errors, but has a negative impact on performance and energy consumption. We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a hardware Transactional Memory (HTM)-based error recovery mechanism. The policy applies dynamic voltage scaling (DVS) (while keeping frequency fixed) based on the feedback provided by HTM, which makes it simple and generally applicable. Experiments on an embedded platform show our technique capable of 57% energy improvement compared to using voltage guardbands and an extra 21-24% improvement over existing state-of-the-art error tolerance solutions, at a nominal area and time overhead. © 2017 acm.

关键词： Energy efficiency Energy conservation Energy utilization Errors hardware Reliability Semiconductor devices Storage allocation (computer) Voltage scaling Dynamic voltage scaling (DVS) Error recovery mechanisms Error tolerance hardware transactional memory Operating frequency Performance improvements Transactional memory Variability

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An efficient hardware design for cerebellar models using approximate circuits: special session paper 17

An efficient hardware design for cerebellar models using app...

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Proceedings of the Twelfth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Honglan Jiang Leibo Liu Jie Han University of Alberta Edmonton AB Canada Tsinghua University Beijing China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： multiplier cerebellar model approximate circuits adder

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2010 IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2010: Foreword

2010 IEEE/ACM/IFIP International Conference on Hardware/Soft...

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2010 IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2010 2010年 iii页

作者： Givargis, Tony Donlin, Adam

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Remote detection of unauthorized activity via spectral analysis: work-in-progress 17

Remote detection of unauthorized activity via spectral analy...

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Proceedings of the Twelfth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Fatih Karabacak Umit Ogras Sule Ozev Arizona State University

ISBN: (纸本)9781450351850

Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enter the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operation bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.

关键词： EM emission hardware/firmware trojan detection IoT security

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Exploring fast and slow memories in HMP core types: work-in-progress 17

Exploring fast and slow memories in HMP core types: work-in-...

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Proceedings of the Twelfth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Bryan Donyanavard Amir Mahdi Hosseini Monazzah Tiago Mück Nikil Dutt University of California Sharif University of Technology

ISBN: (纸本)9781450351850

Studies have shown memory and computational needs vary independently across applications. Recent work has explored using hybrid memory technology (SRAM+NVM) in on-chip memories of multicore processors (CMPs) to support the varied needs of diverse workloads. Such works suggest architectural modifications that require supplemental management in the memory hierarchy. Instead, we propose to deploy hybrid memory in a manner that integrates seamlessly with the existing heterogeneous multicore (HMP) architectural model, and therefore does not require any architectural modification, simply the integration of different memory technologies on-chip. We evaluate platforms with a combination of fast (SRAM cache) and slow (STT-MRAM cache) core-types for mobile workloads.

关键词： SPM scratchpad memory hardware/software memory management many-core architectures virtualization

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