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Efficient Design Space Exploration by Knowledge Transfer 16

Efficient Design Space Exploration by Knowledge Transfer

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Li, Dandan Wang, Senzhang Yao, Shuzhen Liu, Yu-Hang Cheng, Yuanqi Sun, Xian-He Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Comp Sci & Technol Nanjing Jiangsu Peoples R China Collaborat Innovat Ctr Novel Software Technol & I Nanjing Jiangsu Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China IIT Dept Comp Sci Chicago IL 60616 USA

ISBN: (纸本)9781450344838

Due to the exponentially increasing size of design space of microprocessors and time-consuming simulations, predictive models have been widely employed in design space exploration (DSE). Traditional approaches mostly build a program-specific predictor that needs a large number of program-specific samples. Thus considerable simulation cost is required for each program. In this paper, we study the novel problem of transferring knowledge from the labeled samples of previous programs to help predict the responses of the new target program whose labeled samples are very sparse. Inspired by the recent advances of transfer learning, we propose a transfer learning based DSE framework TrDSE to build a more efficient and effective predictive model for the target program with only a few simulations by borrowing knowledge from previous programs. Specifically, TrDSE includes two phases: 1) clustering the programs based on the proposed orthogonal array sampling and the distribution related features, and 2) with the guidance of clustering results, predicting the responses of configurations in design space of the target program by a transfer learning based regression algorithm. We evaluate the proposed TrDSE on the benchmarks of SPEC CPU 2006 suite. The results demonstrate that the proposed framework is more efficient and effective than state-of-art DSE techniques.

关键词： Design space exploration Processor design Knowledge transfer

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Optimal Functional-Unit Assignment and Buffer Placement for Probabilistic Pipelines 16

Optimal Functional-Unit Assignment and Buffer Placement for ...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Weiwen Sha, Edwin H. -M. Zhuge, Qingfeng Chen, Xianzhang Chongqing Univ Coll Comp Sci Chongqing Peoples R China

ISBN: (纸本)9781450344838

Applications, such as streaming applications, modeled by task graphs can be efficiently executed in a pipelined fashion. In synthesizing application-specific heterogeneous pipelined systems, where to place buffers (called buffer placement) and what type of functional units to execute each task (called functional assignment) are two critical problems. In reality, the execution time of each task may not be fixed, which makes the above two problems much more challenging. In this paper, we model the execution time of each task on different types of functional units as a random variable. Our objective is to obtain the optimal functional assignment and buffer placement, such that the resultant pipeline can satisfy the timing requirement with the minimum cost under the guaranteed confidence probability. This paper presents efficient algorithms to achieve the objective. Experiments show that other techniques cannot find any feasible solutions in many cases while ours can. Even for the cases where they can find feasible solutions, our algorithms achieve the minimum cost which gives a significant reduction on the total cost, compared with existing techniques.

关键词： High-level synthesis application-specific system optimal algorithms probabilistic scenario

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Enabling the High Level synthesis of Data Analytics Accelerators 16

Enabling the High Level Synthesis of Data Analytics Accelera...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Minutoli, Marco Castellana, Vito Giovanni Tumeo, Antonino Lattuada, Marco Ferrandi, Fabrizio Pacific Northwest Natl Lab High Performance Comp Richland WA 99352 USA Politecn Milan Dipartimento Elettron Informaz & Bioingn I-20132 Milan Italy

ISBN: (纸本)9781450344838

Conventional High Level synthesis (HLS) tools mainly target compute intensive kernels typical of digital signal processing applications. We are developing techniques and architectural templates to enable HLS of data analytics applications. These applications are memory intensive, present fine-grained, unpredictable data accesses, and irregular, dynamic task parallelism. We discuss an architectural template based around a distributed controller to efficiently exploit thread level parallelism. We present a memory interface that supports parallel memory subsystems and enables implementing atomic memory operations. We introduce a dynamic task scheduling approach to efficiently execute heavily unbalanced workload. The templates are validated by synthesizing queries from the Lehigh University Benchmark (LUBM), a well know SPARQL benchmark.

关键词： High level synthesis

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Build your Own VR system an introduction to VR displays and cameras for hobbyists and educators 17

Build your Own VR system an introduction to VR displays and ...

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acm SIGGRAPH 2017 Courses - international conference on Computer Graphics and Interactive Techniques, SIGGRAPH 2017

作者： Wetzstein, Gordon Konrad, Robert Ikoma, Hayato Padmanaban, Nitish Stanford University United States

ISBN: (纸本)9781450350143

Wearable computing is widely anticipated to be the next computing platform for consumer electronics and beyond. In many wearable computing applications, most notably virtual and augmented reality (VR/AR), the primary interface between a wearable computer and a user is a near-eye display. A near-eye display in turn is only a small part of a much more complex system that delivers these emerging VR/AR experiences. Other key components of VR/AR systems include low-latency tracking of the user's head position and orientation, magnifying optics, sound synthesis, and also content creation. In can be challenging to understand all of these technologies in detail as only limited and fragmented educational material on the technical aspects of VR/AR exist today. The proposed SIGGRAPH course serves as a comprehensive introduction to VR/AR technology to conference attendees. It is based on a quarterlong class taught to undergraduate and graduate students at Stanford. The Stanford class (EE 267: Virtual Reality) is a lab-based maker-focused experience that teaches students how to build a head-mounted display (HMD) from scratch in 10 weeks. Every week, a different component is taught and implemented, including the graphics pipeline, stereo rendering, lens distortion with fragment shaders, head orientation tracking with inertial measurement units, positional tracking, spatial sound, and cinematic VR content creation. At the end, the students will have built a VR display from scratch and implemented every part of it. We intend to bring this experience to SIGGRAPH and teach conference attendees the same in a 3.25 h course. All hardware components are low-cost and off-the-shelf;the list will be shared with attendees. For maximum accessibility, all software is implemented in WebGL and using the Arduino platform. Source code will be provided to conference attendees. At the end of the SIGGRAPH course, attendees will leave with a detailed understanding of VR displays and cameras and they w

关键词： Students

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How to Enable software Isolation and Boost system Performance with Sub-block Erase over 3D Flash Memory 16

How to Enable Software Isolation and Boost System Performanc...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Chang, Hsin-Yu Ho, Chien-Chung Chang, Yuan-Hao Chang, Yu-Ming Kuo, Tei-Wei Macronix Int Co Ltd Hsinchu Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Res Ctr Informat Technol Innovat Taipei Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan

ISBN: (纸本)9781450344838

The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability problem, that is already severe to 3D flash memory. In this work, we propose a sub-block erase design to not only alleviate the write amplification problem by reducing live-page copying but also improve the system reliability with a software isolation strategy. In particular, sub-blocks are carefully allocated to satisfy write requests so as to reduce disturbance by using free or invalid sub-blocks as isolation layers among sub-blocks, without additional hardware cost and capacity loss. A series of experiments were conducted to evaluate the capability of the proposed design. The results show that the proposed design is very effective in improving the system performance by reducing garbage collection overheads and in improving the device reliability/lifetime.

关键词： Flash memory

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An Accurate and Flexible Early Memory system Power Evaluation Approach Using a Microcomponent Method 16

An Accurate and Flexible Early Memory System Power Evaluatio...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Chen, Chi-Kang Wu, Hsin-I Hsiao, Chi-Ting Tsay, Ren-Song Natl Tsing Hua Univ Dept Comp Sci Hsinchu Taiwan Ind Technol Res Inst Hsinchu Taiwan

ISBN: (纸本)9781450344838

As energy efficiency has become a primary concern, system designers have greater need for a flexible and highly accurate power estimation method for evaluating different architecture options. Since memory is an increasingly dominant power consumer, we reexamine existing memory power models and propose a highly efficient microcomponent-based approach with data-aware refinement for accurate system-level power estimations. The key contribution of our approach is that the proposed microcomponent method allows designers to use flexible architecture compositions. Our approach identifies the common microcomponents used by internal memory commands and accurately pre-calibrates the power consumption pattern of each microcomponent. We decompose target design architectures into these microcomponents to easily derive accurate power estimates. To achieve very high accuracy, we consider the data variation effect by leveraging the fact that memory circuit is mainly doing data passing and hence a simple interpolation technique can further boost accuracy. Our experiments show that the proposed approach produces accurate results of less than 2% error rate in average for system power analysis.

关键词： Energy efficiency

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Conquering MPSoC Complexity with Principles of a Self-Aware Information Processing Factory 16

Conquering MPSoC Complexity with Principles of a Self-Aware ...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Dutt, Nikil Kurdahi, Fadi J. Ernst, Rolf Herkersdorf, Andreas Univ Calif Irvine Ctr Embedded & Cyber Phys Syst Irvine CA 92697 USA Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Tech Univ Munich D-80290 Munich Germany

ISBN: (纸本)9781450344838

We introduce the idea of an Information Processing Factory as a step towards autonomous many-core platforms in Cyber-Physical systems (CPS) and the Internet of Things (IoT). It represents a paradigm shift in platform design moving long term, with robust and independent platform operation in the focus of platform-centric design rather than existing semiconductor device or software technology, as mostly seen today. Such a refocus is not only needed to prepare for the time when technology scaling comes to an end, but is a necessity to manage complexity when networked IT systems not only by far outnumber humans but when their complexity by far exceeds that of human societies. While such applications complexity growth is visible to large parts of the society, and is publicly discussed, it is important to note that the complexity growth equally affects the platforms (computers, communication, storage, etc.) which enable such growing applications. This challenge is partly addressed by the new areas of Cyber-Physical systems and the Internet-of-Things, but the changing challenges to the operation of complex microelectronic systems is mostly left to computer and software architects, and to semiconductor technology. This perspective paper motivates the necessity for a paradigm shift in IT system design and its application to autonomous systems as a main application.

关键词： Self-awareness system-on-Chip cyber-physical systems

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Scalable and Realistic Benchmark synthesis for Efficient NoC Performance Evaluation: A Complex Network Analysis Approach 16

Scalable and Realistic Benchmark Synthesis for Efficient NoC...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Xue, Yuankun Bogdan, Paul Univ Southern Calif 3740 McClintock Ave Los Angeles CA 90007 USA

ISBN: (纸本)9781450344838

The complexity of the design-space exploration of large-scale NoCs is exacerbated not only by the ever-increasing number of cores, but also by the increased runtime uncertainties in both the scale and task structure of the emerging applications. Consequently, it is crucial to develop rigorous mathematical frameworks for capturing the task dependencies of varied applications to foster the generation of realistic benchmarks that can guide the NoC design. However, the current NoC benchmark suites either lack portability and poorly scale as they require intensive development efforts on specific architectures and simulation time, or are synthesized based on purely stochastic models that are disconnected with real applications, which may easily lead to biased and/or delayed design choices. To overcome these drawbacks, we propose a benchmark synthesis framework that i) not only allows extraction of dynamical task dependencies of the application and synthesize traffic workloads spatio-temporally consistent with realistic traffic behavior, ii) but can also be easily scaled by the proposed complex network inspired algorithm for large benchmark generation while preserving key structural features that governs application communication behaviors. We validate the proposed framework on a large-scale simulation environment by running a set of real applications. Experimental results show that the synthesized benchmarks respect the traffic patterns of the original applications and preserve key features of application task structures.

关键词： Network-on-chip

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Partial FPGA Bitstream Encryption Enabling hardware DRM in Mobile Environments 16

Partial FPGA Bitstream Encryption Enabling Hardware DRM in M...

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acm international conference on Computing Frontiers (CF)

作者： Barbareschi, Mario Cilardo, Alessandro Mazzeo, Antonino Univ Naples Federico II Dept Elect Engn & Informat Technol CeRICT Scrl Ctr Reg Informat Commun Technol Via Claudio 21 I-80125 Naples Italy

ISBN: (纸本)9781450341288

The concept of digital right management (DRM) has become extremely important in current mobile environments. This paper shows how partial bitstream encryption can allow the secure distribution of hardware applications resembling the mechanisms of traditional software DRM. Building on the recent developments towards the secure distribution of hardware cores, the paper demonstrates a prototypical implementation of a user mobile device supporting such distribution mechanisms. The prototype extends the Android operating system with support for hardware reconfigurability and showcases the interplay of novel security concepts enabled by hardware DRM, the advantages of a design flow based on high-level synthesis, and the opportunities provided by current software-rich reconfigurable systems-onChips. Relying on this prototype, we also collected extensive quantitative results demonstrating the limited overhead incurred by the secure distribution architecture.

关键词： system-on-chip

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Time in Cyber-Physical systems 16

Time in Cyber-Physical Systems

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Shrivastava, Aviral Derler, Patricia Li Baboud, Ya-Shian Stanton, Kevin Khayatian, Mohammad Andrade, Hugo A. Weiss, Marc Eidson, John Chandhoke, Sundeep Arizona State Univ Tempe AZ 85287 USA Natl Instruments Austin TX USA Intel Corp Santa Clara CA 95051 USA Natl Inst Stand & Technol Gaithersburg MD 20899 USA Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781450344838

Many modern cyber-physical systems (CPS), especially industrial automation systems, require the actions of multiple computational systems to be performed at much higher rates and more tightly synchronized than is possible with ad hoc designs. Time is the common entity that computing and physical systems in CPS share, and correct interfacing of that is essential to flawless functionality of a CPS. Fundamental research is needed on ways to synchronize clocks of computing systems to a high degree, and on design methods that enable building blocks of CPS to perform actions at specified times. To realize the potential of CPS in the coming decades, suitable ways to specify distributed CPS applications are needed, including their timing requirements, ways to specify the timing of the CPS components (e.g. sensors, actuators, computing platform), timing analysis to determine if the application design is possible using the components, confident top-down design methodologies that can ensure that the system meets its timing requirements, and ways and methodologies to test and verify that the system meets the timing requirements. Furthermore, strategies for securing timing need to be carefully considered at every CPS design stage and not simply added on. This paper exposes these challenges of CPS development, points out limitations of previous approaches, and provides some research directions towards solving these challenges.

关键词： Cyber Physical system

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