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Conquering MPSoC complexity with principles of a self-aware information processing factory

Conquering MPSoC complexity with principles of a self-aware ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Nikil Dutt Fadi J. Kurdahi Rolf Ernst Andreas Herkersdorf Center for Embedded & Cyber-physical Systems Univ. of California Irvine CA USA Technische Universität Braunschweig Germany Technical University of Munich Germany

ISBN: (纸本)9781509035908

We introduce the idea of an Information Processing Factory as a step towards autonomous many-core platforms in Cyber-Physical systems (CPS) and the Internet of Things (IoT). It represents a paradigm shift in platform design moving long term, with robust and independent platform operation in the focus of platform-centric design rather than existing semiconductor device or software technology, as mostly seen today. Such a refocus is not only needed to prepare for the time when technology scaling comes to an end, but is a necessity to manage complexity when networked IT systems not only by far outnumber humans but when their complexity by far exceeds that of human societies. While such applications complexity growth is visible to large parts of the society, and is publicly discussed, it is important to note that the complexity growth equally affects the platforms (computers, communication, storage, etc.) which enable such growing applications. This challenge is partly addressed by the new areas of Cyber-Physical systems and the Internet-of-Things, but the changing challenges to the operation of complex microelectronic systems is mostly left to computer and software architects, and to semiconductor technology. This perspective paper motivates the necessity for a paradigm shift in IT system design and its application to autonomous systems as a main application.

关键词： Production facilities IP networks Microelectronics hardware Information processing system-on-chip Safety

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A practical methodology to validate the statistical behavior of Bloom filters

A practical methodology to validate the statistical behavior...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Venkateshwar Kottapalli Sunil Khatri Dept. of Electrical & Computer Engineering Texas A&M University College Station TX USA

ISBN: (纸本)9781509035908

Bloom filters are commonly used to test for set membership. A Bloom filter consists of a series of hash functions, whose combined signature is used to construct a composite hash. Applications are broad, and include networking, transactional memory, server load balancing etc. Several realizations, both in hardware and software, have been proposed in academia and industry, but a reliable means to empirically test the statistical behavior of Bloom filters is lacking. In this paper, we present an efficient, practical methodology to validate the statistical performance of Bloom filters. This paper does not focus on the design of a new Bloom filter. Our scheme is based on the use of the NIST test suite, which is a widely accepted means to test for randomness in the cryptography community. In particular, we first test the randomness of the hash functions that comprise the Bloom filter in isolation, and then test for randomness of the Bloom filter, which is constructed by combining the hash functions. We also prove that randomness is a sufficient condition for the uniformity of the hash function and the Bloom filter output. Finally, we test our approach using two classes of Bloom filters, and based on the results, we provide practical guidelines for designing Bloom filters.

关键词： Memory management NIST Robustness Cryptography hardware Industries Data structures

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Zero and data reuse-aware fast convolution for deep neural networks on GPU

Zero and data reuse-aware fast convolution for deep neural n...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hyunsun Park Dongyoung Kim Junwhan Ahn Sungjoo Yoo Department of EE POSTECH Department of CSE Seoul National University Department of EE Seoul National University

ISBN: (纸本)9781509035908

Convolution operations dominate the total execution time of deep convolutional neural networks (CNNs). In this paper, we aim at enhancing the performance of the state-of-the-art convolution algorithm (called Winograd convolution) on the GPU. Our work is based on two observations: (1) CNNs often have abundant zero weights and (2) the performance benefit of Winograd convolution is limited mainly due to extra additions incurred during data transformation. In order to exploit abundant zero weights, we propose a low-overhead and efficient hardware mechanism that skips multiplications that will always give zero results regardless of input data (called ZeroSkip). In addition, to leverage the second observation, we present data reuse optimization for addition operations in Winograd convolution (called AddOpt), which improves the utilization of local registers, thereby reducing on-chip cache accesses. Our experiments with a real-world deep CNN, VGG-16, on GPGPU-Sim and Titan X show that the proposed methods, ZeroSkip and AddOpt, achieve 51.8% higher convolution performance than the baseline Winograd convolution. Moreover, even without any hardware modification, AddOpt alone gives 35.6% higher performance on a real hardware platform, Titan X.

关键词： Convolution Graphics processing units hardware Neural networks Kernel Convolutional codes Memory management

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Multiform logical time for me/mo-codesign 16

Multiform logical time for me/mo-codesign

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Proceedings of the 14th acm-IEEE international conference on Formal Methods and Models for system Design

作者： Robert de Simone INRIA France

ISBN: (纸本)9781509027910

There is now a consistent corpus of models and methods for software/hardware codesign (scope of MeMoCoDe). Still, while success is quite established at both ends of the spectrum (High-Level hardware synthesis, and system Engineering), the adoption of such software modeling approach inside mainstream software Engineering communities could easily be improved. This is certainly so because some of the principles of application modeling do not exactly match, or elsewhere do not focus upon the same concerns, as traditional coding style. Putting forth the relevant important concepts for application modeling, while investigating their relevance to traditional engineering experience, is certainly a way to counter confusion. We view the notion of Multiform Logical Time as such a fundamental *** a first part of the talk we consider the premises of Multiform Logical Time in Embedded Design (its origin, its relevance at places of design flows); in a second part we introduce a small declarative language to express logical time properties, study its expressiveness and its associated analysis techniques.

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Realizing erase-free SLC flash memory with rewritable programming design

Realizing erase-free SLC flash memory with rewritable progra...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Yu-Ming Chang Yung-Chun Li Ping-Hsien Lin Hsiang-Pang Li Yuan-Hao Chang Macronix International Co. Ltd. Emerging System Lab. Hsinchu 300 Taiwan R.O.C. Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C. Institute of Information Science Academia Sinica Taipei Taiwan R.O.C.

ISBN: (纸本)9781509035908

Over the past years, the adaptation of flash memory has seen a tremendous growth in a wide range of fields, with high-end applications demanding ever higher reliability and performance for storage devices. Even though a single-level-cell (SLC) flash memory can have a higher endurance and a lower access latency to better meet that requirement in comparison with a multi-level-cell (MLC) one, the rapid deterioration of reliability due to advanced shrinking technology means that a flash block can only survive over a smaller and smaller number of erase cycles. This work proposes an erase-free scheme, which comprises the design of rewritable programming and software management, to enable a rewritable usage model that can reuse flash blocks several times without using erase operations in an SLC flash memory based storage system. The evaluation results show that the proposed scheme achieves 6-time rewritable capability such that 83% erase operations can be removed; in the best settings, the write latency can be reduced by 3.67× on average under various workloads.

关键词： Programming Threshold voltage Error correction codes Reliability engineering Memory management hardware

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FPGA-Based Parallel Implementation of SURF Algorithm 22

FPGA-Based Parallel Implementation of SURF Algorithm

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22nd IEEE international conference on Parallel and Distributed systems (ICPADS)

作者： Chen, Wenjie Ding, Shuaishuai Chai, Zhilei He, Daojing Zhang, Weihua Zhang, Guanhua Peng, Qiwei Luo, Wang East China Normal Univ MoE Engn Res Ctr Software Hardware Codesign Techn Shanghai 200062 Peoples R China Jiangnan Univ Sch IoT Engn Wuxi 214122 Peoples R China State Key Lab Math Engn & Adv Comp Wuxi 214125 Peoples R China Fudan Univ Parallel Proc Inst Shanghai 200433 Peoples R China NARI Grp Corp State Grid Elect Power Res Inst Nanjing 211000 Jiangsu Peoples R China

ISBN: (纸本)9781509044573

SURF (Speeded up robust features) detection is used extensively in object detection, tracking and matching. However, due to its high complexity, it is usually a challenge to perform such detection in real time on a general-purpose processor. This paper proposes a parallel computing algorithm for the fast computation of SURF, which is specially designed for FPGAs. By efficiently exploiting the advantages of the architecture of an FPGA, and by appropriately handling the inherent parallelism of the SURF computation, the proposed algorithm is able to significantly reduce the computation time. Our experimental results show that, for an image with a resolution of 640x480, the processing time for computing using SURF is only 0.047 seconds on an FPGA (XC6SLX150T, 66.7 MHz), which is 13 times faster than when performed on a typical i3-3240 CPU (with a 3.4 GHz main frequency) and 249 times faster than when performed on a traditional ARM system (CortexTM-A8, 1 GHz).

关键词： SURF FPGA parallel computing High Level synthesis

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Runtime configurable deep neural networks for energy-accuracy trade-off

Runtime configurable deep neural networks for energy-accurac...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hokchhay Tann Soheil Hashemi R. Iris Bahar Sherief Reda School of Engineering Brown University Providence RI

ISBN: (纸本)9781509035908

We present a novel dynamic configuration technique for deep neural networks that permits step-wise energy-accuracy tradeoffs during runtime. Our configuration technique adjusts the number of channels in the network dynamically depending on response time, power, and accuracy targets. To enable this dynamic configuration technique, we co-design a new training algorithm, where the network is incrementally trained such that the weights in channels trained in earlier steps are fixed. Our technique provides the flexibility of multiple networks while storing and utilizing one set of weights. We evaluate our techniques using both an ASIC-based hardware accelerator as well as a low-power embedded GPGPU and show that our approach leads to only a small or negligible loss in the final network accuracy. We analyze the performance of our proposed methodology using three well-known networks for MNIST, CIFAR-10, and SVHN datasets, and we show that we are able to achieve up to 95% energy reduction with less than 1% accuracy loss across the three benchmarks. In addition, compared to prior work on dynamic network reconfiguration, we show that our approach leads to approximately 50% savings in storage requirements, while achieving similar accuracy.

关键词： hardware Runtime Training Memory management Neurons Neural networks Convolution

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Scalable and realistic benchmark synthesis for efficient NoC performance evaluation: A complex network analysis approach

Scalable and realistic benchmark synthesis for efficient NoC...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Yuankun Xue Paul Bogdan University of Southern California Los Angeles USA

ISBN: (纸本)9781509035908

The complexity of the design-space exploration of large-scale NoCs is exacerbated not only by the ever-increasing number of cores, but also by the increased runtime uncertainties in both the scale and task structure of the emerging applications. Consequently, it is crucial to develop rigorous mathematical frameworks for capturing the task dependencies of varied applications to foster the generation of realistic benchmarks that can guide the NoC design. However, the current NoC benchmark suites either lack portability and poorly scale as they require intensive development efforts on specific architectures and simulation time, or are synthesized based on purely stochastic models that are disconnected with real applications, which may easily lead to biased and/or delayed design choices. To overcome these drawbacks, we propose a benchmark synthesis framework that i) not only allows extraction of dynamical task dependencies of the application and synthesize traffic workloads spatio-temporally consistent with realistic traffic behavior, ii) but can also be easily scaled by the proposed complex-network inspired algorithm for large benchmark generation while preserving key structural features that governs application communication behaviors. We validate the proposed framework on a large-scale simulation environment by running a set of real applications. Experimental results show that the synthesized benchmarks respect the traffic patterns of the original applications and preserve key features of application task structures.

关键词： Benchmark testing Mathematical model Runtime Stochastic processes Heuristic algorithms Complex networks Computer architecture

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A design to reduce write amplification in object-based NAND flash devices

A design to reduce write amplification in object-based NAND ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jie Guo Chuhan Min Tao Cai Yiran Chen Department of Electrical and Computer Engineering University of Pittsburgh School of Computer Science and Telecommunication Engineering Jiangsu University

ISBN: (纸本)9781509035908

Write amplification is a major cause of performance and endurance degradations in NAND flash based storage systems. In an object-based NAND flash device, two causes of write amplification are onode partial update and cascading update. Updating one onode, a kind of small-sized object metadata, invokes partial page update (i.e., onode partial update) that incurs unnecessary migration of the un-updated data. An cascading update denotes that object metadata is updated in a cascading manner due to erase-before-program property of NAND flash memory. In this work, we propose a system design to alleviate onode partial update and cascading update. The proposed system design includes: 1) A multi-level garbage collection technique to minimize unnecessary data migration incurred by onode partial update; 2) A B+ table tree and selective cache design to reduce the write operations associated with cascading update; and 3) A power failure handling technique to guarantee system consistency. Experiment results show that our proposed design can achieve up to 20% write reduction compared to the best state-of-the-art.

关键词： Metadata Indexes system analysis and design Memory management Random access memory Resource management

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An accurate and flexible early memory system power evaluation approach using a microcomponent method

An accurate and flexible early memory system power evaluatio...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chi-Kang Chen Hsin-I Wu Chi-Ting Hsiao Ren-Song Tsay Industrial Technology Research Institute Hsinchu Taiwan Department of Computer Science National Tsing-Hua University Hsinchu Taiwan

ISBN: (纸本)9781509035908

As energy efficiency has become a primary concern, system designers have greater need for a flexible and highly accurate power estimation method for evaluating different architecture options. Since memory is an increasingly dominant power consumer, we reexamine existing memory power models and propose a highly efficient microcomponent-based approach with data-aware refinement for accurate system-level power estimations. The key contribution of our approach is that the proposed microcomponent method allows designers to use flexible architecture compositions. Our approach identifies the common microcomponents used by internal memory commands and accurately pre-calibrates the power consumption pattern of each microcomponent. We decompose target design architectures into these microcomponents to easily derive accurate power estimates. To achieve very high accuracy, we consider the data variation effect by leveraging the fact that memory circuit is mainly doing data passing and hence a simple interpolation technique can further boost accuracy. Our experiments show that the proposed approach produces accurate results of less than 2% error rate in average for system power analysis.

关键词： Integrated circuit modeling Random access memory Power demand Memory management Timing Computational modeling Estimation

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