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A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory

A disturbance-aware sub-block design to improve reliability ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hung-Sheng Chang Yuan-Hao Chang Tei-Wei Kuo Yu-Ming Chang Hsiang-Pang Li Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C. Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C. lnstitute of Information Science Academia Sinica Taipei Taiwan R.O.C. Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan R.O.C.

ISBN: (纸本)9781509035908

The reliability problem of modern flash-memory chips quickly deteriorates because of the nature of MLC chips. Although the vertical stacking of storage cells in 3D flash-memory chips dramatically increases the bit density, compared to 2D chips, it also results in severe disturbance problems. In this work, we propose to create sub-blocks in the MTD layer by considering different program disturb resistance patterns, without any hardware cost. In particular, a disturbance-aware sub-block design is proposed to utilize the hotness information of data to further improve the reliability of 3D MLC flash memory by smartly choosing sub-blocks to use when extra information is available from the flash translation layer. The proposed design was evaluated by a series of experiments over traces from SNIA. It was shown that the disturb errors could be reduced by at least 50% under DFTL and BL, i.e., a page-level FTL and a block-level FTL design, compared to the conventional MLC programming designs.

关键词： Three-dimensional displays Reliability engineering Resistance Programming Logic gates Error correction codes

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Efficient design space exploration by knowledge transfer

Efficient design space exploration by knowledge transfer

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Dandan Li Senzhang Wang Shuzhen Yao Yu-Hang Liu Yuanqi Cheng Xian-He Sun School of Computer Science and Engineering Beihang University Beijing China College of Computer Science and Technology Nanjing University of Aeronautics and Astronautics Nanjing China Collaborative Innovation Center of Novel Software Technology and Industrialization Nanjing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Illinois Institute of Technology Chicago USA

ISBN: (纸本)9781509035908

Due to the exponentially increasing size of design space of microprocessors and time-consuming simulations, predictive models have been widely employed in design space exploration (DSE). Traditional approaches mostly build a program-specific predictor that needs a large number of program-specific samples. Thus considerable simulation cost is required for each program. In this paper, we study the novel problem of transferring knowledge from the labeled samples of previous programs to help predict the responses of the new target program whose labeled samples are very sparse. Inspired by the recent advances of transfer learning, we propose a transfer learning based DSE framework TrDSE to build a more efficient and effective predictive model for the target program with only a few simulations by borrowing knowledge from previous programs. Specifically, TrDSE includes two phases: 1) clustering the programs based on the proposed orthogonal array sampling and the distribution related features, and 2) with the guidance of clustering results, predicting the responses of configurations in design space of the target program by a transfer learning based regression algorithm. We evaluate the proposed TrDSE on the benchmarks of SPEC CPU 2006 suite. The results demonstrate that the proposed framework is more efficient and effective than state-of-art DSE techniques.

关键词： Predictive models Knowledge transfer Clustering algorithms Feature extraction Prediction algorithms Training data Space exploration

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hardware synthesis from a Recursive Functional Language

Hardware Synthesis from a Recursive Functional Language

引用

IEEE/acm international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Zhai, Kuangya Townsend, Richard Lairmore, Lianne Kim, Martha A. Edwards, Stephen A. Columbia Univ New York NY 10027 USA

ISBN: (纸本)9781467383219

An Abstraction in hardware description languages stalled at the register-transfer level decades ago, yet few alternatives have had much success, in part because they provide only modest gains in expressivity. We propose to make a much larger jump: a compiler that synthesizes hardware from behavioral functional specifications. Our compiler translates general Haskell programs into a restricted intermediate representation before applying a series of semantics-preserving transformations, concluding with a simple syntax-directed translation to systemVerilog. Here, we present the overall framework for this compiler, focusing on the intermediate representations involved and our method for translating general recursive functions into equivalent hardware. We conclude with experimental results that depict the performance and resource usage of the circuitry generated with our compiler.

关键词： Functional hardware Recursion High-Level synthesis

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Human-machine communication for assistive IoT technologies

Human-machine communication for assistive IoT technologies

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Alexandra Porter Md Muztoba Umit Y. Ogras School of Electrical Computer and Energy Engineering Arizona State University

ISBN: (纸本)9781509035908

Despite the phenomenal advances in the computational power and functionality of electronic systems, human-machine interaction has largely been limited to simple control panels, keyboard, mouse and display. Consequently, these systems either rely critically on close human guidance or operate almost independently from the user. An exemplar technology integrated tightly into our lives is the smartphone. However, the term “smart” is a misnomer, since it has fundamentally no intelligence to understand its user. The users still have to type, touch or speak (to some extent) to express their intentions in a form accessible to the phone. Hence, intelligent decision making is still almost entirely a human task. A life-changing experience can be achieved by transforming machines from passive tools to agents capable of understanding human physiology and what their user wants [1]. This can advance human capabilities in unimagined ways by building a symbiotic relationship to solve real world problems cooperatively. One of the high-impact application areas of this approach is assistive internet of things (IoT) technologies for physically challenged individuals. The Annual World Report on Disability reveals that 15% of the world population lives with disability, while 110 to 190 million of these people have difficulty in functioning [1]. Quality of life for this population can improve significantly if we can provide accessibility to smart devices, which provide sensory inputs and assist with everyday tasks. This work demonstrates that smart IoT devices open up the possibility to alleviate the burden on the user by equipping everyday objects, such as a wheelchair, with decision-making capabilities. Moving part of the intelligent decision making to smart IoT objects requires a robust mechanism for human-machine communication (HMC). To address this challenge, we present examples of multimodal HMC mechanisms, where the modalities are electroencephalogram (EEG), speech commands, and mot

关键词： virtualisation control engineering computing decision making electroencephalography human-robot interaction Internet of Things medical computing medical robotics smart phones Virtualization control engineering computing Internet of things Smartphone Human machine interaction medical computing medical robotics Electroencephalography Intelligent decision making decision making hardware motion compensation world population disability

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A parallelizable approach for mining likely invariants

A parallelizable approach for mining likely invariants

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IEEE/acm international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Danese, Alessandro Piccolboni, Luca Pravadelli, Graziano Univ Verona Str Grazie 15 I-37134 Verona Italy

ISBN: (纸本)9781467383219

A relevant aspect in design analysis and verification is monitoring how logic relations among different variables change at run time. Current static approaches suffer from scalability problems that prevent their adoption on large designs. On the contrary, dynamic techniques scale better from the memory-consumption point of view. However, to achieve a high accuracy, they require to analyse a huge number of ( long) execution traces, which results in time-consuming phases. In this paper, we present a new efficient approach to automatically infer logic relations among the variables of a design implementation. Both a sequential and a GPU-oriented parallel implementation are proposed to dynamically extract likely invariants from execution traces on different time windows. Execution traces composed of millions of simulation instants can be efficiently analysed.

关键词： data mining graphics processing units hardware-software codesign GPU-oriented parallel implementation design analysis design verification dynamic techniques execution traces likely invariants mining logic relations memory-consumption view point parallelizable approach scalability problems sequential parallel implementation static approaches time windows time-consuming phases Accuracy Analytical models Computer architecture Engines Graphics processing units Instruction sets Instruments design analysis instruction sets design verification Time windows hardware/software co-design Computer Architecture Graphics Processing Unit Engines ANALYSIS MODELS data mining Legal Executions time phase Invariant

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The Shift to Multicores in Real-Time and Safety-Critical systems

The Shift to Multicores in Real-Time and Safety-Critical Sys...

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IEEE/acm international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Saidi, Selina Ernst, Rolf Uhrig, Sascha Theiling, Henrik de Dinechin, Benoit Dupont Tech Univ Carolo Wilhelmina Braunschweig Braunschweig Germany Airbus Grp Innovat Leiden Netherlands SYSGO AG Mainz Germany Kalray SA Montbonnot St Martin France

ISBN: (纸本)9781467383219

In real-time and safety-critical systems, the move towards multicores is becoming unavoidable in order to keep pace with the increasing required processing power and to meet the high integration trend while maintaining a reasonable power consumption. However, standard multicore systems are mainly designed to increase average performance, whereas embedded systems have additional requirements with respect to safety, reliability and realtime behavior. Therefore, the shift to multicores raises several challenges the embedded community has to face. These challenges involve the design of certifiable multicore platforms, the management of shared resources and the development/integration of parallel software. These issues are encountered at different steps of system development, from modeling and design to software implementation and hardware deployment. Therefore, both multicore/semiconductor manufacturers and the real-time community have to bridge the gap in order to meet the challenges imposed by multicores. The goal of this paper is to trigger such a discussion as an attempt to bridge the gap between the two worlds and to raise awareness about the hurdles and challenges that need to be tackled.

关键词： embedded systems parallel processing power aware computing resource allocation safety-critical software certifiable multicore platform design hardware deployment multicore systems parallel software development parallel software integration real-time system safety-critical system shared resource management software implementation system development Aerospace electronics hardware Multicore processing Real-time systems Safety software Timing safety-critical software real-time systems Embedded systems power aware computing software implementation avionics systems development computer software management of resources Computer hardware PARALLEL PROCESSING (COMPUTERS) Resource utilization Consumer safety safety software design

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Computer Security by hardware-Intrinsic Authentication

Computer Security by Hardware-Intrinsic Authentication

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IEEE/acm international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hoffman, Caio Cortes, Mario Aranha, Diego F. Araujo, Guido Univ Estadual Campinas Inst Comp Campinas SP Brazil

ISBN: (纸本)9781467383219

The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things ( IoT), has raised a number of challenges for the design of systems-on-Chip ( SoCs) devices. Tiny manufacturing costs, stringent security, and ultra-low power operation constraints have considerably raised SoC design requirements. More than incremental approaches which try to re-use current cryptographic mechanisms, the new generation of IoT devices will require novel solutions which deeply integrate their hardware-intrinsic features to program execution. This paper proposes a low-cost PUF-based authentication architecture aiming to secure code execution in IoT SoCs. The solution is deeply embedded into the processor micro-architecture, so as to minimize re-design costs and performance penalties. This new architecture model not only deals with the most common threats against code and data authenticity and integrity, but also provides an approach to extract from processor's caches a stable and unpredictable key that is used in the code and data authentication process.

关键词： Internet of Things authorisation cache storage computer architecture cryptography data integrity system-on-chip Internet of the things IoT SoC computer security cryptographic mechanisms daily-life objects data authentication process data authenticity electronic devices hardware-intrinsic authentication hardware-intrinsic features low-cost PUF-based authentication architecture processor caches processor microarchitecture systems-on-chip device design Authentication Computer architecture Cryptography Performance evaluation Random access memory software Computer Architecture Data Quality cryptography Computer Security system-on-chip Electron devices random access machine cache storage Internet of things Authentication Authorization Performance Evaluation computer software

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Completeness Bounds and Sequentialization for Model Checking of Interacting Firmware and hardware

Completeness Bounds and Sequentialization for Model Checking...

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IEEE/acm international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Ahn, Sunha Malik, Sharad Gupta, Aarti Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781467383219

An emerging trend in system design is to implement complex system management functions in firmware ( FW). This changing design scenario requires support for verifying FW in the context of its hardware ( HW) environment. As shown in previous work, there is value in a unified HW-FW model for driving the verification tasks. This model can help identify specific commonly-occurring interaction patterns between the HW and FW. These patterns enable pruning the verification search space as demonstrated in previous work in automating FW test generation using concolic testing. In this work, we introduce a bounded model checking ( BMC)-based methodology for FW verification. Although BMC is effective for finding bugs by unrolling the underlying transition system up to some bound, it requires a completeness threshold on the bound to ensure complete verification. We show how commonly occurring FW code patterns can be exploited, using inexpensive static analysis techniques, to determine this completeness bound. Further, we show how this bound analysis, combined with the interaction patterns in the unified HW-FW model, is used to sequentialize the concurrent FW and HW code, i. e., to derive a sequential program that represents the parallel interaction of the FW and HW. This enables the direct application of standard software model checkers such as CBMC on this sequentialized program. We have automated this process by implementing: ( i) a static completeness bound analyzer on top of the tool Frama-C, and ( ii) a sequentializer to generate code for verification by the CBMC model checker. We evaluate the resulting tool using three real FW benchmarks, each consisting of a Linux device driver and its interacting QEMU-emulated HW code with multiple correctness properties. We successfully computed the BMC completeness bounds for 41 out of 46 properties and completed model checking for 12 out of 16 FW transactions.

关键词： Firmware

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Control-flow guided property directed reachability for imperative synchronous programs 16

Control-flow guided property directed reachability for imper...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Xian Li Klaus Schneider Department of Computer Science University of Kaiserslautern Germany

ISBN: (纸本)9781509027910

Property directed reachability (PDR) has been introduced as a very efficient verification method for synchronous hardware circuits that is based on induction rather than fixpoint iteration. However, hardware circuits are usually synthesized from more abstract high-level languages like synchronous languages (or synchronous subsets of hardware description languages). In this paper, we show that it is possible to derive from such high-level languages additional control-flow information that can be added to the transition relation to make PDR even more efficient. As will be shown, PDR can benefit from this additional information since many safety properties become inductive only with respect to the enhanced transition relations. The added control-flow information is not needed for the synthesis and is therefore not explicitly encoded in the generated systems, but it can be easily derived from the original programs and used for verification. We present two methods to compute additional control-flow information that differ in how precisely they approximate the reachable control-flow states and also in the runtime required for their computation.

关键词： hardware Model checking Safety software Handheld computers High level languages Computational modeling

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Design methodologies for securing cyber-physical systems

Design methodologies for securing cyber-physical systems

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international conference on hardware/software codesign and system synthesis, CODES+ISSS 2015

作者： Faruque, Mohammad Al Regazzoni, Francesco Pajic, Miroslav Dept. of Electrical Engineering and Computer Science University of California IrvineCA United States ALaRI Institute University of Lugano Lugano Switzerland Dept. of Electrical and Computer Engineering Duke University Durham NC United States

ISBN: (纸本)9781467383219

Cyber-Physical systems (CPS) are in most cases safety- and mission-critical. Standard design techniques used for securing embedded systems are not suitable for CPS due to the restricted computation and communication budget available in the latter. In addition, the sensitivity of sensed data and the presence of actuation components further increase the security requirements of CPS. To address these issues, it is necessary to provide new design methods in which security is considered from the beginning of the whole design flow and addressed in a holistic way. In this paper, we focus on the design of secure CPS as part of the complete CPS design process, and provide insights into new requirements on platform-aware design of control components, design methodologies and architectures posed by CPS design. We start by discussing methods for the multi-disciplinary modeling, simulation, tools, and software synthesis challenges for CPS. We also present a framework for design of secure control systems for CPS, while taking into account properties of the underlying computation and communication platforms. Finally, we describe the security challenges in the computing hardware that is used in CPS. © 2015 IEEE.

关键词： Cyber Physical system

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