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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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Power-awareness and smart-resource management in embedded computing systems

Power-awareness and smart-resource management in embedded co...

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IEEE/acm international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Santambrogio, M. D. Ayala, Jose L. Campanoni, Simone Cattaneo, R. Durelli, G. C. Ferroni, M. Nacci, A. Pagan, J. Zapater, M. Vallejo, M. Politecn Milan DEIB I-20133 Milan Italy Univ Complutense Madrid DACYA E-28040 Madrid Spain Northwestern Univ EELS Evanston IL USA UPM CCS Madrid Spain Univ Nacl Colombia Dept Elect Energy Automat Grp UNAL Bogota Colombia Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy Univ Complutense Madrid DACYA Ctr Computat Simulat E-28040 Madrid Spain Univ Nacl Colombia Dept Elect Energy Automat Grp UNAL Bogota Colombia

ISBN: (纸本)9781467383219

Resources such as quantities of transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer science abstractions have not changed since the 1960's. Therefore this is the time for a fresh approach to the way systems are designed and used.

关键词： embedded systems power aware computing computer science abstraction embedded computing system power-awareness smart-resource management Accuracy Distortion Multicore processing Parallel processing Program processors Runtime Semantics power aware computing Program processors Embedded computing Runtime PARALLEL PROCESSING (COMPUTERS) Embedded systems Semantics abnormal shapes distortion semiotics

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Run-DMC: Runtime Dynamic Heterogeneous Multicore Performance and Power Estimation for Energy Efficiency

Run-DMC: Runtime Dynamic Heterogeneous Multicore Performance...

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IEEE/acm international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Muck, Tiago Sarma, Santanu Dutt, Nikil Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA

ISBN: (纸本)9781467383219

In this paper we propose Run-DMC, an accurate runtime performance and power estimation scheme for dynamic workloads executing on heterogeneous multicore systems. In contrast to previous works, Run-DMC uses fine grain per-thread metrics that model the Thread Load Contribution ( TLC) induced by the native OS scheduling policy to accurately predict performance and power for any possible thread-to-core mapping. This allows the operating system to opportunistically exploit the heterogeneous multicore architecture by dynamically mapping workloads to the most appropriate core type. We have integrated our models into the Linux kernel running on top of a heterogeneous multicore system with 4 different core types. Our experimental results show that Run-DMC models yield up to 97% more energy efficient when compared to the vanilla Linux. When compared to the approach employed by state-of-the-art energy-aware schedulers, Run-DMC yields up-to 44% better energy efficiency.

关键词： Linux energy conservation multi-threading multiprocessing systems power aware computing processor scheduling Linux kernel OS scheduling policy TLC dynamic mapping workloads energy efficiency fine grain per-thread metrics heterogeneous multicore architecture heterogeneous multicore systems operating system power estimation run-DMC runtime dynamic heterogeneous multicore performance thread load contribution thread-to-core mapping vanilla Linux Estimation Instruction sets Load modeling Measurement Multicore processing Runtime Sensors power estimation Energy efficiency power aware computing instruction sets Runtime Operating systems Linux Multiprocessing systems Multithreading scheduling of multiprocessor Load modeling Energy conservation Multi-core processors Sensors core type

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C-To-Verilog Translation Validation 15

C-To-Verilog Translation Validation

引用

2015 acm/IEEE international conference on Formal Methods and Models for codesign (MEMOCODE)

作者： Leung, Alan Bounov, Dimitar Lerner, Sorin Univ Calif San Diego La Jolla CA 92093 USA

ISBN: (纸本)9781509002375

To offset the high engineering cost of digital circuit design, hardware engineers are looking increasingly toward high-level languages such as C and C++ to implement their designs. To do this, they employ High-Level synthesis (HLS) tools that translate their high-level specifications down to a hardware description language such as Verilog. Unfortunately, HLS tools themselves employ sophisticated optimization passes that may have bugs that silently introduce errors in realized hardware. The cost of such errors is high, as hardware is costly or impossible to repair if software patching is not an option. In this work, we present a translation validation approach for verifying the correctness of the HLS translation process. Given an initial C program and the generated Verilog code, our approach establishes their equivalence without relying on any intermediate results or representations produced by the HLS tool. We implemented our approach in a tool called VTV that is able to validate a body of programs compiled by the Xilinx Vivado HLS compiler.

关键词： hue lightness saturation hardware design languages Computer hardware high level language(hll) Translation Process Carbon

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CONVINCE: A cross-layer modeling, exploration and validation framework for next-generation connected vehicles

CONVINCE: A cross-layer modeling, exploration and validation...

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IEEE international conference on Computer-Aided Design

作者： Bowen Zheng Chung-Wei Lin Huafeng Yu Hengyi Liang Qi Zhu University of California Riverside Riverside CA Toyota lnto Technoloqv Center Mountain View CA Boeing Research & Technology Huntsville AL

ISBN: (纸本)9781509034215

Next-generation autonomous and semi-autonomous vehicles will not only precept the environment with their own sensors, but also communicate with other vehicles and surrounding infrastructures for vehicle safety and transportation efficiency. The design, analysis and validation of various vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) applications involve multiple layers, from V2V/V2I communication networks down to software and hardware of individual vehicles, and concern with stringent requirements on multiple metrics such as timing, security, reliability and fault tolerance. To cope with these challenges, we have been developing CONVINCE, a cross-layer modeling, exploration and validation framework for connected vehicles. The framework includes mathematical models, synthesis and validation algorithms, and a heterogeneous simulator for inter-vehicle communications and intra-vehicle software and hardware in a holistic environment. It explores various design options with respect to constraints and objectives on system safety, security, reliability, cost, etc. A V2V application is used in the case study to demonstrate the effectiveness of the proposed framework.

关键词： Vehicles Timing Analytical models Computational modeling software Security Mathematical model

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Big/Little Deep Neural Network for Ultra Low Power Inference

Big/Little Deep Neural Network for Ultra Low Power Inference

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IEEE/acm international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Park, Eunhyeok Kim, Dongyoung Kim, Soobeom Kim, Yong-Deok Kim, Gunhee Yoon, Sungroh Yoo, Sungjoo Seoul Natl Univ Comp Memory Architecture Lab Seoul 151 South Korea Samsung Elect Device Solut Software R&D Ctr Suwon South Korea Seoul Natl Univ Vis & Learning Lab Seoul 151 South Korea Seoul Natl Univ Adv Comp Lab Seoul 151 South Korea

ISBN: (纸本)9781467383219

Deep neural networks ( DNNs) have recently proved their effectiveness in complex data analyses such as object/speech recognition. As their applications are being expanded to mobile devices, their energy efficiencies are becoming critical. In this paper, we propose a novel concept called big/LITTLE DNN ( BL-DNN) which significantly reduces energy consumption required for DNN execution at a negligible loss of inference accuracy. The BL-DNN consists of a little DNN ( consuming low energy) and a full-fledged big DNN. In order to reduce energy consumption, the BL-DNN aims at avoiding the execution of the big DNN whenever possible. The key idea for this goal is to execute the little DNN first for inference ( without big DNN execution) and simply use its result as the final inference result as long as the result is estimated to be accurate. On the other hand, if the result from the little DNN is not considered to be accurate, the big DNN is executed to give the final inference result. This approach reduces the total energy consumption by obtaining the inference result only with the little, energy-efficient DNN in most cases, while maintaining the similar level of inference accuracy through selectively utilizing the big DNN execution. We present design-time and runtime methods to control the execution of big DNN under a trade-off between energy consumption and inference accuracy. Experiments with state-of-the-art DNNs for ImageNet and MNIST show that our proposed BL-DNN can offer up to 53.7% ( ImageNet) and 94.1% ( MNIST) reductions in energy consumption at a loss of 0.90% ( ImageNet) and 0.12% ( MNIST) in inference accuracy, respectively.

关键词： Deep neural network low power

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Evaluating and Exploiting Impacts of Dynamic Power Management Schemes on system Reliability

Evaluating and Exploiting Impacts of Dynamic Power Managemen...

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international conference on Compilers, Architecture and synthesis for Embedded systems (CASES)

作者： Lai, Liangzhen Chandra, Vikas Gupta, Puneet Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA ARM Res Leesburg VA USA

ISBN: (纸本)9781467383202

hardware reliability has been a major concern for nano-scale computing systems. Different hardware design choices, application workloads and software management schemes can jointly affect the system's resilience. In this paper, we first develop a hardware evaluation platform based on an embedded/mobile development board and standard Linux kernel. We demonstrate the use of our platform to evaluate the system's power and radiation-induced soft error rate in presence of system power management schemes and with different application workloads and various hardware design configurations. We also propose system/cloud-based virtual sensing to capture varying ambient conditions for reliability evaluation. New reliability management policies are proposed and implemented in Linux kernel to exploit the flexibility in different existing power management schemes. We demonstrate that our policies can achieve the system reliability target under varying application workloads and ambient conditions. Experiments show that our policies are efficient and with less than 3% additional power overhead compared to the optimal schemes characterized offline.

关键词： Power Management Soft Error Operating system Linux Kernel

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A Unified hardware/software MPSoC system Construction and Run-Time Framework

A Unified Hardware/Software MPSoC System Construction and Ru...

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conference on Design Automation Test in Europe (DATE)

作者： Skalicky, Sam Schmidt, Andrew G. Lopez, Sonia French, Matthew Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA Univ So Calif Inst Informat Sci Los Angeles CA USA

ISBN: (纸本)9783981537048

With the continual enhancement of heterogeneous resources in FPGA devices, utilizing these resources becomes a challenging burden for developers. Especially with the inclusion of sophisticated multiple processor system-on-chips, the necessary skill set to effectively leverage these resources spans both hardware and software expertise. The maturation of high level synthesis tools and programming languages aim to alleviate these complexities, yet there still exist systematic gaps that must be bridged to provide a more cohesive hardware/software development environment. High level MPSoC design initiatives such as Redsharc have reduced the costs of entry, simplifying application implementation. We propose a unified hardware/software framework for system construction, leveraging Redsharc's APIs, efficient on-chip interconnects, and run-time controllers. We present system level abstractions that enable compilation and implementation tools for hardware and software to be merged into a single configurable system development environment. Finally, we demonstrate our proposed framework with Redsharc, using AES encryption/decryption spanning software implementations on ARM and MicroBlaze processors and hardware kernels.

关键词： system-on-chip

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GP-based Methodology for HW/SW Co-synthesis of Multiprocessor Embedded systems with Increasing Number of Individuals Obtained by Mutation 5

GP-based Methodology for HW/SW Co-synthesis of Multiprocesso...

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5th international conference on Pervasive and Embedded Computing and Communication systems (PECCS)

作者： Gorski, Adam Ogorzalek, Maciej Jagiellonian Univ Cracow Dept Informat Technol Reymonta 4 Krakow Poland

ISBN: (纸本)9789897581373

In this work, a genetic programming methodology for co-synthesis of multiprocessor systems is presented. Genotype is a tree which nodes include system construction procedures. Thus the design methodology is evolving. Next generations are obtained using genetic operators: mutation, reproduction and crossover. Unlike other algorithms in presented methodology number of individuals obtained by mutation operator is not const. Therefore number of individuals in each population is increasing. The size of final generation is found by the algorithm.

关键词： Embedded systems Genetic Programming Genetic Algorithm Architecture hardware/software Co-Design Multiprocessor system

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Transparent linking of compiled software and synthesized hardware

Transparent linking of compiled software and synthesized har...

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conference on Design Automation Test in Europe (DATE)

作者： Thomas, David B. Fleming, Shane T. Constantinides, George A. Ghica, Dan R. Imperial Coll London Dept Elect & Elect Engn London England Univ Birmingham Sch Comp Sci Birmingham B15 2TT W Midlands England

ISBN: (纸本)9783981537048

Modern heterogeneous devices contain tightly coupled CPU and FPGA logic, allowing low latency access to accelerators. However, designers of the system need to treat accelerated functions specially, with device specific code for instantiating, configuring, and executing accelerators. We present a system level linker, which allows functions in hardware and software to be linked together to create heterogeneous systems. The linker works with post-compilation and post-synthesis components, allowing the designer to transparently move functions between devices simply by linking in either hardware or software object files. The linker places no special emphasis on the software, allowing computation to be initiated from within hardware, with function calls to software to provide services such as file access. A strong type-system ensures that individual code artifacts can be written using the conventions of that domain (C, HLS, VHDL), while allowing direct and transparent linking.

关键词： Computation theory

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hardware synthesis from a recursive functional language 15

Hardware synthesis from a recursive functional language

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Kuangya Zhai Richard Townsend Lianne Lairmore Martha A. Kim Stephen A. Edwards Columbia University

ISBN: (纸本)9781467383219

Abstraction in hardware description languages stalled at the register-transfer level decades ago, yet few alternatives have had much success, in part because they provide only modest gains in expressivity. We propose to make a much larger jump: a compiler that synthesizes hardware from behavioral functional specifications. Our compiler translates general Haskell programs into a restricted intermediate representation before applying a series of semantics-preserving transformations, concluding with a simple syntax-directed translation to systemVerilog. Here, we present the overall framework for this compiler, focusing on the intermediate representations involved and our method for translating general recursive functions into equivalent hardware. We conclude with experimental results that depict the performance and resource usage of the circuitry generated with our compiler.

关键词： hardware Program processors Transforms Algorithm design and analysis IP networks Pattern matching

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