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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是281-290 订阅

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Proceedings of the 12th acm international conference on Computing Frontiers, CF 2015

Proceedings of the 12th ACM International Conference on Comp...

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12th acm international conference on Computing Frontiers, CF 2015

ISBN: (纸本)9781450333580

The proceedings contain 65 papers. The topics discussed include: an empirical high level performance model for future many-cores;just-in-time component-wise power and thermal modeling;an instrumentation approach for hardware-agnostic software characterization;near threshold cloud processors for dark silicon mitigation: the impact on emerging scale-out workloads;data access optimization in a processing-in-memory system;genesis: a language for generating synthetic training programs for machine learning;a significance-driven programming framework for energy-constrained approximate computing;an evaluation and analysis of graph processing frameworks on five key issues;optimizing irregular applications for energy and performance on the tilera many-core architecture;hierarchical synthesis of quantum and reversible architectures;and cooperative repair based on tree structure for multiple failures in distributed storage systems with regenerating codes.

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Keynote talk II: Accelerating data centers using reconfigurable logic

Keynote talk II: Accelerating data centers using reconfigura...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Derek Chiou University of Texas At Austin

Reconfigurable logic has the potential to provide hardware level performance with the flexibility of software. Such properties make it an interesting solution in data center environments that value high throughput, low latency, low power, and uniformity of hardware. Microsoft has been exploring the use of reconfigurable logic in its data centers. In this talk, I will describe some of our efforts in this area.

关键词： Acceleration Field programmable gate arrays Computer architecture hardware Team working Computer simulation system analysis and design

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The shift to multicores in real-time and safety-critical systems 15

The shift to multicores in real-time and safety-critical sys...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Selma Saidi Rolf Ernst Sascha Uhrig Henrik Theiling Benoît Dupont de Dinechin Technische Universität Braunschweig Airbus Group Innovations SYSGO AG Mainz Germany Kalray SA

ISBN: (纸本)9781467383219

In real-time and safety-critical systems, the move towards multicores is becoming unavoidable in order to keep pace with the increasing required processing power and to meet the high integration trend while maintaining a reasonable power consumption. However, standard multicore systems are mainly designed to increase average performance, whereas embedded systems have additional requirements with respect to safety, reliability and realtime behavior. Therefore, the shift to multicores raises several challenges the embedded community has to face. These challenges involve the design of certifiable multicore platforms, the management of shared resources and the development/integration of parallel software. These issues are encountered at different steps of system development, from modeling and design to software implementation and hardware deployment. Therefore, both multi-core/semiconductor manufacturers and the real-time community have to bridge the gap in order to meet the challenges imposed by multicores. The goal of this paper is to trigger such a discussion as an attempt to bridge the gap between the two worlds and to raise awareness about the hurdles and challenges that need to be tackled.

关键词： Multicore processing software Aerospace electronics Safety hardware Timing Real-time systems

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Computer security by hardware-intrinsic authentication 15

Computer security by hardware-intrinsic authentication

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Caio Hoffman Mario Cortes Diego F. Aranha Guido Araujo Institute of Computing University of Campinas

ISBN: (纸本)9781467383219

The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things (IoT), has raised a number of challenges for the design of systems-on-Chip (SoCs) devices. Tiny manufacturing costs, stringent security, and ultra-low power operation constraints have considerably raised SoC design requirements. More than incremental approaches which try to re-use current cryptographic mechanisms, the new generation of IoT devices will require novel solutions which deeply integrate their hardware-intrinsic features to program execution. This paper proposes a low-cost PUF-based authentication architecture aiming to secure code execution in IoT SoCs. The solution is deeply embedded into the processor micro-architecture, so as to minimize re-design costs and performance penalties. This new architecture model not only deals with the most common threats against code and data authenticity and integrity, but also provides an approach to extract from processor's caches a stable and unpredictable key that is used in the code and data authentication process.

关键词： Computer architecture Authentication Cryptography Performance evaluation software Random access memory

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C-to-Verilog translation validation

C-to-Verilog translation validation

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Alan Leung Dimitar Bounov Sorin Lerner University of California San Diego

To offset the high engineering cost of digital circuit design, hardware engineers are looking increasingly toward high-level languages such as C and C++ to implement their designs. To do this, they employ High-Level synthesis (HLS) tools that translate their high-level specifications down to a hardware description language such as Verilog. Unfortunately, HLS tools themselves employ sophisticated optimization passes that may have bugs that silently introduce errors in realized hardware. The cost of such errors is high, as hardware is costly or impossible to repair if software patching is not an option. In this work, we present a translation validation approach for verifying the correctness of the HLS translation process. Given an initial C program and the generated Verilog code, our approach establishes their equivalence without relying on any intermediate results or representations produced by the HLS tool. We implemented our approach in a tool called VTV that is able to validate a body of programs compiled by the Xilinx Vivado HLS compiler.

关键词： hardware design languages hardware Semantics Syntactics Program processors Protocols Ports (Computers)

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Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs 15

Lightweight virtual memory support for many-core accelerator...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Pirmin Vogel Andrea Marongiu Luca Benini Integrated Systems Laboratory ETH Zurich Switzerland Electrical Electronic and Information Engineering University of Bologna Italy

ISBN: (纸本)9781467383219

While high-end heterogeneous systems are increasingly supporting heterogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous system Architecture (HSA) foundation, their low-power counterparts targeting the embedded domain still lack basic features like virtual memory support for accelerators. As opposed to simply passing virtual address pointers, explicit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance. In this work, we present a mixed hardware/software solution to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded systems-on-chip (SoCs). Based on an input/output translation lookaside buffer (IOTLB), efficiently managed by a kernel-level driver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units. Using our evaluation platform based on the Xilinx Zynq-7000 SoC with a many-core accelerator implemented in the programmable logic, we demonstrate the effectiveness of our solution and the benefits of virtual memory support for embedded heterogeneous SoCs.

关键词： Kernel Memory management Programming hardware Random access memory Complexity theory Prefetching

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Transparent and portable agent based task migration for data-flow applications on multi-tiled architectures 15

Transparent and portable agent based task migration for data...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ashaf El-Antably Olivier Gruber Frederic Rousseau Nicolas Fournel TIMA lab - CNRS/UJF/Grenoble INP Grenoble France LIG - CNRS/UJF/Grenoble INP Grenoble France

ISBN: (纸本)9781467383219

Fully distributed memory multi-processors (MPSoC) implemented in multi-tiled architectures are promising solutions to support modern sophisticated applications, however, reliability of such systems is always an issue. As a result, system-level solution like task migration keeps its importance. Transferring the execution of a task from one tile to another helps keep acceptable reliability of such systems. A tile contains at least one processor and associated peripherals with a communication device responsible for inter-tile communications. We propose in this work a task migration technique that targets data-flow applications running on multi-tiled architectures. This technique uses a middleware layer that makes it transparent to application programmers and eases its portability over different multi-tiled architectures. It can be deployed on small operating systems that support neither MMU nor dynamic loading for task code. We show that this technique is operational on x86 based real hardware platform. Experimental results show low overhead both in memory and performance without much variance.

关键词： Context Operating systems Memory architecture hardware Loading Runtime

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Design methodologies for securing cyber-physical systems 15

Design methodologies for securing cyber-physical systems

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mohammad Al Faruque Francesco Regazzoni Miroslav Pajic Dept. of Electrical Engineering & Computer Science University of California Irvine CA USA ALaRI Institute University of Lugano Lugano Switzerland Dept. of Electrical and Computer Engineering Duke University Durham NC USA

ISBN: (纸本)9781467383219

Cyber-Physical systems (CPS) are in most cases safety- and mission-critical. Standard design techniques used for securing embedded systems are not suitable for CPS due to the restricted computation and communication budget available in the latter. In addition, the sensitivity of sensed data and the presence of actuation components further increase the security requirements of CPS. To address these issues, it is necessary to provide new design methods in which security is considered from the beginning of the whole design flow and addressed in a holistic way. In this paper, we focus on the design of secure CPS as part of the complete CPS design process, and provide insights into new requirements on platform-aware design of control components, design methodologies and architectures posed by CPS design. We start by discussing methods for the multi-disciplinary modeling, simulation, tools, and software synthesis challenges for CPS. We also present a framework for design of secure control systems for CPS, while taking into account properties of the underlying computation and communication platforms. Finally, we describe the security challenges in the computing hardware that is used in CPS.

关键词： Analytical models Computational modeling Biological system modeling Computer security Process control Control systems

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Uncertainty-Aware Reliability Analysis and Optimization

Uncertainty-Aware Reliability Analysis and Optimization

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conference on Design Automation Test in Europe (DATE)

作者： Khosravi, Faramarz Mueller, Malte Glass, Michael Teich, Juergen Univ Erlangen Nurnberg Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9783981537048

Due to manufacturing tolerances and aging effects, future embedded systems have to cope with unreliable components. The intensity of such effects depends on uncertain aspects like environmental or usage conditions such that highly safety-critical systems are pessimistically designed for worst-case mission profiles. In this work, we propose to explicitly model the uncertain characteristics of system components, i.e. we model components using reliability functions with parameters distributed between a best and worst case. Since destructive effects like temperature may affect several components simultaneously (e.g. those in the same package), a correlation between uncertainties of components exists. The proposed uncertainty-aware method combines a formal analysis approach and a Monte Carlo simulation to consider uncertain characteristics and their different correlations. It delivers a holistic view on the system's reliability with best/worst/averagecase behavior and also insights on variance and quantiles. But, existing optimization approaches typically assume design objectives to be single values or to follow a predefined distribution. As a remedy, we propose a dominance criterion for meta-heuristic optimization approaches like evolutionary algorithms that enables the comparison of system implementations with arbitrarily distributed characteristics. Our presented experimental results show that (a) the proposed analysis comes at low overhead while capturing existing uncertainties with sufficient accuracy, and (b) the optimization process is significantly enhanced when guiding the search process by additional aspects like variance and the 95% quantile, delivering better system implementations as found by an uncertainty-oblivious optimization approach.

关键词： Optimization

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dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations 15

dsReliM: Power-constrained reliability management in Dark-Si...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mohammad Salehi Muhammad Shafique Florian Kriebel Semeen Rehman Mohammad Khavari Tavana Alireza Ejlali Jörg Henkel Karlsruhe Institute of Technology (KIT) Germany Department of Computer Engineering Sharif University of Technology Tehran Iran Department of Electrical and Computer Engineering George Mason University Fairfax Virginia USA

ISBN: (纸本)9781467383219

Due to the tight power envelope, in the future technology nodes it is envisaged that not all cores in a many-core chip can be simultaneously powered-on (at full performance level). The power-gated cores are referred to as Dark Silicon. At the same time, growing reliability issues due to process variations and soft errors challenge the cost-effective deployment of future technology nodes. This paper presents a reliability management system for Dark Silicon chips (dsReliM) that optimizes for reliability of on-chip systems while jointly accounting for soft errors, process variations and the thermal design power (TDP) constraint. Towards the TDP-constrained reliability optimization, dsReliM leverages multiple reliable application versions that can potentially execute on different cores with frequency variations and supporting differenst voltage-frequency levels, thus facilitating distinct power, reliability and performance tradeoffs at run time. Experiments show that our dsReliM system provides up to 20% reliability improvements under different TDP constraints when compared to a state-of-the-art technique. Also, compared to an ideal-case optimal solution, dsReliM deviates up to 2.5% in terms of reliability efficiency, but speeds up the reliability management decision time by a factor of up to 3100.

关键词： software reliability software Silicon Timing Management Transient analysis

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