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Completeness bounds and sequentialization for model checking of interacting firmware and hardware 15

Completeness bounds and sequentialization for model checking...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sunha Ahn Sharad Malik Aarti Gupta Princeton University

ISBN: (纸本)9781467383219

An emerging trend in system design is to implement complex system management functions in firmware (FW). This changing design scenario requires support for verifying FW in the context of its hardware (HW) environment. As shown in previous work, there is value in a unified HW-FW model for driving the verification tasks. This model can help identify specific commonly-occurring interaction patterns between the HW and FW. These patterns enable pruning the verification search space as demonstrated in previous work in automating FW test generation using concolic testing. In this work, we introduce a bounded model checking (BMC)-based methodology for FW verification. Although BMC is effective for finding bugs by unrolling the underlying transition system up to some bound, it requires a completeness threshold on the bound to ensure complete verification. We show how commonly occurring FW code patterns can be exploited, using inexpensive static analysis techniques, to determine this completeness bound. Further, we show how this bound analysis, combined with the interaction patterns in the unified HW-FW model, is used to sequentialize the concurrent FW and HW code, i.e., to derive a sequential program that represents the parallel interaction of the FW and HW. This enables the direct application of standard software model checkers such as CBMC on this sequentialized program. We have automated this process by implementing: (i) a static completeness bound analyzer on top of the tool Frama-C, and (ii) a sequentializer to generate code for verification by the CBMC model checker. We evaluate the resulting tool using three real FW benchmarks, each consisting of a Linux device driver and its interacting QEMU-emulated HW code with multiple correctness properties. We successfully computed the BMC completeness bounds for 41 out of 46 properties and completed model checking for 12 out of 16 FW transactions.

关键词： Model checking Context Benchmark testing hardware Analytical models Linux Registers

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Big/little deep neural network for ultra low power inference 15

Big/little deep neural network for ultra low power inference

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Eunhyeok Park Dongyoung Kim Soobeom Kim Yong-Deok Kim Gunhee Kim Sungroh Yoon Sungjoo Yoo Computing Memory Architecture Lab Seoul National University Device Solutions Samsung Electronics Software R&D Center Vision and Learning Lab Seoul National University Advanced Computing Lab Seoul National University

ISBN: (纸本)9781467383219

Deep neural networks (DNNs) have recently proved their effectiveness in complex data analyses such as object/speech recognition. As their applications are being expanded to mobile devices, their energy efficiencies are becoming critical. In this paper, we propose a novel concept called big/LITTLE DNN (BL-DNN) which significantly reduces energy consumption required for DNN execution at a negligible loss of inference accuracy. The BL-DNN consists of a little DNN (consuming low energy) and a full-fledged big DNN. In order to reduce energy consumption, the BL-DNN aims at avoiding the execution of the big DNN whenever possible. The key idea for this goal is to execute the little DNN first for inference (without big DNN execution) and simply use its result as the final inference result as long as the result is estimated to be accurate. On the other hand, if the result from the little DNN is not considered to be accurate, the big DNN is executed to give the final inference result. This approach reduces the total energy consumption by obtaining the inference result only with the little, energy-efficient DNN in most cases, while maintaining the similar level of inference accuracy through selectively utilizing the big DNN execution. We present design-time and runtime methods to control the execution of big DNN under a trade-off between energy consumption and inference accuracy. Experiments with state-of-the-art DNNs for ImageNet and MNIST show that our proposed BL-DNN can offer up to 53.7% (ImageNet) and 94.1% (MNIST) reductions in energy consumption at a loss of 0.90% (ImageNet) and 0.12% (MNIST) in inference accuracy, respectively.

关键词： Energy consumption Accuracy Biological neural networks hardware Energy efficiency Neurons Memory management

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How to improve the space utilization of dedup-based PCM storage devices? 15

How to improve the space utilization of dedup-based PCM stor...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chun-Ta Lin Yuan-Hao Chang Tei-Wei Kuo Hung-Sheng Chang Hsiang-Pang Li Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C. Institute of Information Science Academia Sinica Taipei Taiwan R.O.C. Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan R.O.C. Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C.

ISBN: (纸本)9781467383219

There is a growing demand to introduce more and more intelligence to storage devices in recent years, especially with the rapid increasing of hardware computing power. This paper targets on essential design issues in space utilization for dedup-based non-volatile phase-change memory (PCM). We explore the adoption of data duplication techniques to reduce potential data duplicates over PCM storage devices to provide more storage space than the physical storage space does. Among various data deduplication techniques, variable-sized chunking is considered in less cost-effective PCM-based storage devices because variable-sized chunking has better data deduplication capability than fixed-sized chunking. However, in a typical system architecture, data are written or updated in the fixed management units (e.g., LBAs). Thus, to ultimately improve the space utilization of PCM-based storage device, the technical problem falls on (1) how to map fixed-sized LBAs to variable-sized chunks and (2) how to efficiently manage (i.e., allocated and deallocate) free PCM storage space for variable-sized chunks. In this work, we propose a free space manager, called container-based space manager, to resolve the above two issues by exploiting the fact that (1) a storage system initially has more free space to relax the complexity on space management and (2) the space optimization of a storage system can grow with the time when it contains more and more data. The proposed design is evaluated over popular benchmarks, for which we have very encouraging results.

关键词： Phase change materials Power capacitors Performance evaluation Ash Computer architecture Random access memory Media

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Generating Situation Awareness in Cyber-Physical systems: Creation and Exchange of Situational Information 14

Generating Situation Awareness in Cyber-Physical Systems: Cr...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Preden, Jurgo Tallinn Univ Technol Res Lab Proact Technol Tallinn Estonia

ISBN: (纸本)9781450330510

Cyber-physical systems depend on good situation awareness in order to cope with the changes of the physical world and in the configuration of the system to fulfill their goal functions. Being aware of the situation in the physical world enables a cyber-physical system to adapt its behaviour according to the actual state of the world as perceived by the cyber-physical system. Understanding the situation of the cyber-physical system itself enables adaptation of the behaviour of the system according to the current capabilities and state of the system, e.g., providing less features or features with limited functionality in case some of the system components are not functional. In order to build resilient cyber-physical systems we need to build systems that are able to consider both of these aspects in their operation.

关键词： situation awareness cyber physical system

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HSAemu - A Full system Emulator for HSA Platforms 14

HSAemu - A Full System Emulator for HSA Platforms

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Ding, Jiun-Hung Hsu, Wei-Chung Jeng, Bai-Cheng Hung, Shih-Hao Chung, Yeh-Ching Natl Tsing Hua Univ Hsinchu 30013 Taiwan Natl Taiwan Univ Taipei 10617 Taiwan

ISBN: (纸本)9781450330510

Heterogeneous system Architecture (HSA) is an open industry standard designed to support a large variety of data-parallel and task-parallel programming models. Currently, most of HSA hardware and software components are still in development. It is helpful to provide various heterogeneous simulation environments for HSA developers in developing HSA software stacks. This paper presents the design of HSAemu, a full system emulator for the HSA platform, and illustrates how those HSA features are implemented in the simulator. HSAemu provides an infrastructure of heterogeneous simulation environments by supporting required HSA features, including hUMA, hQ and HSAIL. Based on the infrastructure, HSAemu provide two simulation models, FastSim and DeepSim, for high-speed functional emulation and slow cycle-accurate simulation, respectively. In our preliminary experiments, HSAemu helps test a complete HSA software stack and profile system performance. Our case studies show that HSAemu is very useful as a hardware/software co-design tool for heterogeneous systems.

关键词： HSA GPU simulation parallel simulation

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On-Chip Self-Awareness Using Cyberphysical-systems-On-Chip (CPSoC) 14

On-Chip Self-Awareness Using Cyberphysical-Systems-On-Chip (...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Sarma, S. Dutt, N. Gupta, P. Nicolau, A. Venkatasubramanian, N. Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA

ISBN: (纸本)9781450330510

We presented CPSoC, a self-aware sensor-actuator-rich MPSoC platform that deploys the computation-communication-control codesign of CPS together with cross-layer adaptations to achieve multiple design objectives. The CPSoC paradigm enables on-chip self-awareness (selective or opportunistic) adaptation using the concepts of cross-layer physical and virtual sensing and actuations. In [3] we illustrate CPSoC's potential for self-awareness and cross-layer adaptations using several examples and have developed an FPGA prototype to emulate a typical CPSoC.

关键词： actuators field programmable gate arrays sensors system-on-chip CPSoC paradigm FPGA prototype control-communication-computing system codesign cyberphysical-system-on-chip on-chip cross-layer actuation on-chip cross-layer sensing on-chip self-awareness on-chip sensing physical environment sensor-actuator rich many-core computing platforms Aging Computer architecture Delays Predictive models Quality of service Sensors system-on-chip system-on-chip Field programmable gate arrays Sensors Computer Architecture Quality of service physical environment Prediction models self-awareness actuators Aging Awareness delay

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Automated Firmware Testing using Firmware-hardware Interaction Patterns 14

Automated Firmware Testing using Firmware-Hardware Interacti...

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Ahn, Sunha Malik, Sharad Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781450330510

Firmware is low-level software which can directly access hardware and is often shipped with the hardware platform. This component of the system is increasing in scale and importance, and thus firmware validation is a critical part of system validation. Firmware validation relies on the interacting hardware components which are usually not available until the late design stages. This is generally addressed through co-simulating C/C++ based firmware code and HDL hardware models (including systemC). However, this tends to be slow, and is further exacerbated by the large number of possible interleavings between the concurrent firmware and hardware threads. Typically, in the co-simulation, the scheduler, such as the systemC scheduler, will only explore a single, or at best a small number of possible firmware-hardware interleavings and thus may miss critical bugs. In this paper we present an alternative approach to firmware validation that is based on automatically generating a test-set for the firmware with the goal of complete path coverage while considering its interactions with hardware and other firmware threads. It uses a service-function based Transaction Level Model (TLM) which has been used in the past for firmware hardware codesign. The test generation is based on concolic testing which has been used successfully in software test generation. However, existing concolic testing tools are used for test-generation of sequential code, and cannot directly consider the interaction of other hardware/firmware threads with the target firmware thread during test generation. We address this limitation by exploiting specific interaction patterns between the firmware and hardware threads that can be analyzed from the TLM. We show how these patterns, along with the firmware and hardware threads are used to automatically generate a sequential program that is test-equivalent to the target firmware transaction and that can be used with a standard sequential program concolic test

关键词： firmware hardware-software codesign multi-threading program testing program verification C++ based firmware code Frama-C HDL hardware models KLEE Linux device driver code QEMU emulated hardware code systemC scheduler TLM automated firmware testing concolic testing tools concurrent firmware firmware benchmarks firmware transaction firmware validation firmware-hardware codesign firmware-hardware interaction patterns firmware-hardware interleavings hardware components hardware-firmware thread interaction low-level software multithreaded interactions sequential code test-generation service-function based transaction level model software test generation standard sequential program concolic test generator static code analyzer system validation Benchmark testing Computer bugs Generators hardware Microprogramming software Firmware Computer hardware Trefoil Microprogramming Benchmark testing Multithreading Test generation hardware/software co-design program testing program verification dynamos LOW LEVEL computer software Transmission line measurements system validation

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Keynote talk I: Syntax-guided synthesis

Keynote talk I: Syntax-guided synthesis

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Rajeev Alur University of Pennsylvania Philadelphia PA US

The classical formulation of the program-synthesis problem is to find a program that meets a correctness specification given as a logical formula. Recent work on program synthesis and program optimization illustrates many potential benefits of allowing the user to supplement the logical specification with a syntactic template that constrains the space of allowed implementations. The formulation of the syntax-guided synthesis problem (SyGuS) is aimed at standardizing the core computational problem common to these proposals in a logical framework [1]. The input to the SyGuS problem consists of a background theory, a semantic correctness specification for the desired program given by a logical formula, and a syntactic set of candidate implementations given by a grammar. The computational problem then is to find an implementation from the set of candidate expressions so that it satisfies the specification in the given theory. In this talk, we first describe how a wide range of problems such as automatic synthesis of loop invariants, program optimization, learning programs from examples, and program sketching, can be formalized as SyGuS instances. We then describe three different instantiations of the counter-example-guided-inductive-synthesis (CEGIS) strategy for solving the SyGuS problem. Finally, we discuss our efforts over the past two years on defining the standardized interchange format built on top of SMT-LIB, repository of benchmarks from diverse applications, organization of the annual competition, SyGuS-COMP, of solvers, and experimental evaluation of solution strategies. More information about our project is available at ***. This research is supported by the NSF Expeditions in Computing project ExCAPE (award CCF 1138996).

关键词： Computer science Computers Optimization Syntactics Information science system analysis and design software

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hardware/software Co-design for A Wireless Sensor Network Platform 14

Hardware/Software Co-design for A Wireless Sensor Network Pl...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Hsieh, Chih-Ming Samie, Farzad Srouji, M. Sammer Wang, Manyi Wang, Zhonglei Henkel, Joerg KIT CES Karlsruhe Germany

ISBN: (纸本)9781450330510

Wireless sensor networks have become shared resources providing sensing services to monitor ambient environment. The tasks performed by the sensor nodes and the network structure are becoming more and more complex so that they cannot be handled efficiently by traditional sensor nodes any more. The traditional sensor node architecture, which has software implementation running on a fixed hardware design, is no longer fit to the changing requirements when new applications with complex computation are added to this shared infrastructure due to several reasons. First, the operation behavior changes because of the application requirements and the environmental conditions which makes a fixed architecture not efficient all the time. Second, to collaborate with other already deployed sensor networks and to maintain an efficient network structure, the sensor nodes require flexible communication capabilities. Furthermore, the information required to determine an efficient hardware/software co-design under the system constraints cannot be known a priori. Therefore a platform which can adapt to run-time situations will play an important role in wireless sensor networks. In this paper, we present a hardware/software co-design framework for a wireless sensor platform, which can adaptively change its hardware/software configuration to accelerate complex operations and provides a flexible communication mechanism to deal with complex network structures. We perform real-world measurements on our prototype to analyze its capabilities. In addition, our case studies with prototype implementation and network simulations show the energy savings of the sensor network application by using the proposed design with run-time adaptivity.

关键词： reconfiguration sensor networks hardware accelerator FPGA low power multi-radio

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On the deployment problem of embedded systems

On the deployment problem of embedded systems

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Stefan Kugele Gheorghe Pucea Ramona Popa Laurent Dieudonné Horst Eckardt Institut für Informatik Technische Universität München München Germany Liehherr-Aerospace Lindenherg GmbH Lindenberg Germany Siemens AG Corporate Technology München Germany

The quality of today's embedded systems e. g. in vehicles, airplanes, or automation plants is highly influenced by their architecture. In this context, we study the so-called deployment problem. The question is where (i. e., on which execution unit) to deploy which software application or which sensor/actuator shall be connected to which device in an automation plant. First, we introduce a domain-specific constraint and optimization language fitting the needs of our partners. Second, we investigate different approaches to tackle the deployment problem even for industrial size systems. Therefore, we present different solving strategies using (i) multi-objective evolutionary algorithms, (ii) SMT-based, and (iii) ILP-based solving approaches. Furthermore, a combination of the first two is used. We investigate the proposed methods and demonstrate their feasibility using two realistic systems: a civil flight control system (FCS), and a seawater desalination plant.

关键词： Optimization hardware Embedded systems Safety Automation Aerospace electronics

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