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HEFT: A Hybrid system-Level Framework for Enabling Energy-Efficient Fault-Tolerance in NoC based MPSoCs 14

HEFT: A Hybrid System-Level Framework for Enabling Energy-Ef...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Zou, Yong Pasricha, Sudeep Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80523 USA

ISBN: (纸本)9781450330510

In emerging CMOS process technologies, network-on-chip (NoC) fabrics are increasingly becoming susceptible to transient faults. Fault-tolerance mechanisms that are typically employed in NoCs usually entail significant energy overheads that are expected to become prohibitive as fault rates increase in future CMOS technologies. We propose a system-level framework called HEFT to trade-off energy consumption and fault-tolerance in the NoC fabric. Our hybrid framework tackles the challenge of enabling energy-efficient resilience in NoCs in two phases: at design time and at runtime. At design time, we implement an algorithm to guide the robust mapping of cores on to a die while satisfying application bandwidth and latency constraints. At runtime we devise a prediction algorithm to monitor and detect changes in fault susceptibility of NoC components, to intelligently balance energy consumption and reliability. Experimental results show that HEFT improves energy/reliability ratio of synthesized solutions by 8-20%, while meeting application performance goals, when compared to multiple prior works on reliable system-level NoC design.

关键词： system-level design networks-on-chip fault-tolerance

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system-level memory optimization for high-level synthesis of component-based SoCs 14

System-level memory optimization for high-level synthesis of...

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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

作者： Pilato, Christian Mantovani, Paolo Di Guglielmo, Giuseppe Carloni, Luca P. Department of Computer Science Columbia University New YorkNY United States

ISBN: (纸本)9781450330510

The design of specialized accelerators is essential to the success of many modern systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an accelerator. To address these limitations, we present a novel methodology to automatically derive the memory subsystems of SoC accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the accelerator specifications. We illustrate its effective-ness by presenting experimental results on the design of two accelerators for a high-performance embedded application. Copyright 2014 acm.

关键词： system-on-chip

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Code Generation from a Domain-specific Language for C-based HLS of hardware Accelerators 14

Code Generation from a Domain-specific Language for C-based ...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Reiche, Oliver Schmid, Moritz Hannig, Frank Membarth, Richard Teich, Juergen Friedrich Alexander Univ Erlangen NUrnberg FAU Dept Comp Sci Erlangen Germany Saarland Univ Intel Visual Comp Inst Saarbrucken Germany

ISBN: (纸本)9781450330510

As today's computer architectures are becoming more and more heterogeneous, a plethora of options including CPUs, GPUs, DSPs, reconfigurable logic (FPGAs), and other application-specific processors come into consideration for close-to-sensor processing. Especially, in the domain of image processing on mobile devices, among numerous design challenges, a very stringent energy budget is of utmost importance, making embedded GPUs and FPGAs ideal targets for implementation. Recently, the HIPA(cc) framework was proposed as a means for automatic code generation of image processing algorithms for embedded GPUs, based on a Domain-Specific Language (DSL). Despite of huge advancements in High-Level synthesis (HLS) for FPGAs, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. As a remedy, in this work, we propose code generation techniques for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, numerous high-level transformations, and automatic test bench generation. We evaluate our approach by comparing the resulting hardware accelerators to existing frameworks in terms of performance and resource requirements. Moreover, we assess the achieved energy efficiency in contrast to software implementations, generated by HIPAcc from the same code base, executed on GPUs.

关键词： Code generation domain specific language image processing high-level synthesis hardware accelerator FPCA CPU

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Cost-Effective Design of a Hybrid Electrical Energy Storage system for Electric Vehicles 14

Cost-Effective Design of a Hybrid Electrical Energy Storage ...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Zhu, Di Yue, Siyu Park, Sangyoung Wang, Yanzhi Chang, Naehyuck Pedram, Massoud Univ Southern Calif Los Angeles CA 90089 USA Seoul Natl Univ Seoul South Korea Korea Adv Inst Sci & Technol Daejeon South Korea

ISBN: (纸本)9781450330510

A comprehensive economic feasibility analysis and a cost-driven design methodology are essential to the successful application of hybrid electrical energy storage (BEES) systems in electric vehicles (EVs). This paper thus focuses on designing a cost-effective and high-performance BEES system for EVs, comprising of a supercapacitor bank and a lithium-ion (Li-ion) battery bank. In particular, the paper formulates the capacity provisioning problem for the EV BEES system so as to minimize the total system cost, utilizing accurate models of the battery cycle efficiency and state of health, characteristics of the supercapacitor bank, and dynamics of the EV. The aforesaid problem is subsequently solved by combining a gradient descent-based approach with a simulated annealing-based algorithm. Simulation results show that the proposed EV BEES system achieves 21% lower total cost per day and 30% higher fuel economy compared to a baseline homogeneous electrical energy storage system comprised of Li-ion batteries only.

关键词： Electric vehicles hybrid energy storage systems cost efficiency

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system-of-PUFs: Multilevel Security for Embedded systems 14

System-of-PUFs: Multilevel Security for Embedded Systems

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Konigsmark, S. T. Choden Hwang, Leslie K. Chen, Deming Wong, Martin D. F. Univ Illinois Dept Elect & Comp Engn Champaign IL 61820 USA

ISBN: (纸本)9781450330510

Embedded systems continue to provide the core for a wide range of applications, from smart-cards for mobile payment to smart-meters for power-grids. The resource and power dependency of embedded systems continues to be a challenge for state-of-the-art security practices. Moreover, even theoretically secure algorithms are often vulnerable in their implementation. With decreasing cost and complexity, physical attacks are an increasingly important threat. This threat led to the development of Physically Unclonable Functions (PUFs) which are disordered physical systems with various applications in hardware security. However, consistent security oriented design of embedded systems remains a challenge, as most formalizations and security models are concerned with isolated physical components or high-level concept. We provide four unique contributions: (i) We propose a system-level security model to overcome the chasm between secure components and requirements of high-level protocols;this enables synergy between component-oriented security formalizations and theoretically proven protocols. (ii) An analysis of current practices in PUF protocols using the proposed system-level security model;we identify significant issues and expose assumptions that require costly security techniques. (iii) A system-of-PUF (SoP) that utilizes the large PUF design-space to achieve security requirements with minimal resource utilization;SoP requires 64% less gate-equivalent units than recently published schemes. (iv) A multilevel authentication protocol based on SoP which is validated using our system-level security model and which overcomes current vulnerabilities. Furthermore, this protocol offers breach recognition and recovery.

关键词： Physically Unclonable Functions hardware Authentication

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Metronomy: A Function-Architecture Co-simulation Framework for Timing Verification of Cyber-Physical systems 14

Metronomy: A Function-Architecture Co-simulation Framework f...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Guo, Liangpeng Zhu, Qi Nuzzo, Pierluigi Passerone, Roberto Sangiovanni-Vincentelli, Alberto Lee, Edward A. Univ Calif Berkeley Berkeley CA 94720 USA Univ Calif Riverside Riverside CA 92521 USA Univ Trento Trento TN Italy

ISBN: (纸本)9781450330510

As the design complexity of cyber-physical systems continues to grow, modeling the system at higher abstraction levels with formal models of computation is increasingly appealing since it enables early design verification and analysis. One of the most important aspects in system modeling and analysis is timing. However, it is very challenging to analyze and verify timing at the early design stages, as the design representation is quite abstract and trade-offs have to be made between the performance requirements defined in terms of system functionality and the cost of the feasible architecture that can implement the functionality. In this paper, we present Metronomy, a function-architecture co-simulation framework that integrates functional modeling from Ptolemy and architectural modeling from the Metroll environment via a mapping interface. Metronomy exploits contract theory for timing verification and design space exploration via co-simulation. Two case studies on an electrical power system and a paper-feed sub-system for a high speed printing press demonstrate the effectiveness of our approach.

关键词： Cyber-Physical system Co-simulation Timing

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A Low Cost Acceleration Method for hardware Trojan Detection Based on Fan-out Cone Analysis 14

A Low Cost Acceleration Method for Hardware Trojan Detection...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Zhou, Bin Zhang, Wei Thambipillai, Srikanthan Teo, J. K. J. Nanyang Technol Univ Sch Comp Engn Singapore Singapore Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Harbin Inst Technol Res Ctr Basic Space Sci Harbin Heilongjiang Peoples R China

ISBN: (纸本)9781450330510

Fabless semiconductor industry and government agencies have raised serious concerns about tampering with inserting hardware Trojans in an integrated circuit supply chain in recent years. In this paper, a low hardware overhead acceleration method of the detection of HTs based on the insertion of 2-to-1 MUXs as test points is proposed. In the proposed method, the fact that one logical gate has a significant impact on the transition probability of the logical gates in its logical fan-out cone is utilized to optimize the number of the insertion MUXs. The nets which have smaller transition probability than the threshold value set by the user and minimal logical depth from the primary inputs are selected as the candidate nets. As for each candidate net, only its input net with smallest signal probability is required to be inserted the MUXs based test points until the minimal transition probability of the entire circuit is no smaller than the threshold value. Experiment results on ISCAS'89 benchmark circuits show that our proposed method can achieve remarkable improvement of transition probability with small overhead penalty.

关键词： hardware Trojan Fan-out cone Low cost Signal probability Transition probability

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Dark Silicon as a Challenge for hardware/software Co-Design

Dark Silicon as a Challenge for Hardware/Software Co-Design

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Shafique, Muhammad Garg, Siddharth Mitra, Tulika Parameswaran, Sri Henkel, Joerg Karlsruhe Inst Technol CES Karlsruhe Germany Univ Waterloo Dept ECE Waterloo ON Canada Natl Univ Singapore Sch Comp Singapore Singapore Univ New South Wales Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)9781450330510

Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to stay within the power budget and safe thermal limits, while the other resources will have to be kept powered-off or "dark". In other words, chips will have an abundance of transistors, i.e., more than the number that can be simultaneously powered-on. Heterogeneous computing has been proposed as one way to effectively leverage this abundance of transistors in order to increase performance, energy efficiency and even reliability within power and thermal constraints. However, several critical challenges remain to be addressed including design, automated synthesis, design space exploration and run-time management of heterogeneous dark silicon processors. The hardware/software co-design and synthesis community has potentially much to contribute in solving these new challenges introduced by dark silicon and, in particular, heterogeneous computing. In this paper, we identify and highlight some of these critical challenges, and outline some of our early research efforts in addressing them.

关键词： hardware-software codesign power aware computing automated synthesis design space exploration energy efficiency improvement hardware-software co-design heterogeneous computing heterogeneous dark silicon processors on-chip resources performance improvement power budget power constraint reliability improvement run-time management safe thermal limits thermal constraint transistors Computer architecture hardware Program processors Reliability Silicon Switches hardware/software co-design power budget power aware computing Transistor Device Component Program processors Computer Architecture Silicon Switches performance boost Computer hardware Co-design Space Exploration

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Timing Analysis of Erroneous systems 14

Timing Analysis of Erroneous Systems

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Assare, Omid Gupta, Rajesh Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

ISBN: (纸本)9781450330510

Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of the system, or ensuring controlled occurrence of errors to perform approximate computing. In this paper, we are interested in characterization of error behavior at the level of instructions and programs. We propose Inter- and Intra-Program Variation as measures of error rate variability in different programs and among instructions of a program, respectively. We also characterize the error rate variation caused by the program input data and show that it is comparable to other sources of variability such as process variation. Finally, we present an analysis of the physical location of errors in hardware, identify regions in which most of the errors occur, and how different programs change the distribution of errors among these regions. In order to enable reliable timing analysis of large programs, we propose Clustered Timing Model (CTM), a high level timing model based on clustering functionally similar timing paths of the processor, and develop a CTM for LEON3, a representative in-order RISC processor. The accuracy of the model is verified using our variation-aware timing analysis framework with an average error of 3.9% (max. 6.7%) across a wide range of voltage-temperature corners.

关键词： erroneous systems variability process variation delay faults variation-aware timing analysis dynamic error estimation and software error behavior

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A PCM Translation Layer for Integrated Memory and Storage Management 14

A PCM Translation Layer for Integrated Memory and Storage Ma...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Chang, Bing-Jing Chang, Yuan-Hao Chang, Hung-Sheng Kuo, Tei-Wei Li, Hsiang-Pang Macronix Int Co Ltd Emerging Syst Lab Hsinchu Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Res Ctr Informat Technol Innovat Taipei Taiwan

ISBN: (纸本)9781450330510

Phase change memory (PCM) is known for its potentials as main memory and as storage. In contrast to the past work, this work presents a PCM translation layer that considers how the main memory is used by the operating system together with the usage patterns of storage by trading their performance and reliability. In particular, a joint management scheme is proposed to improve the capability of PCM as both main memory and storage so as to enhance the performance of the entire system. The endurance issue of PCM for main memory is resolved by utilizing the potentially large capacity of the PCM storage space with limited modifications to the existing operating system implementations. Moreover, three commands are proposed to help operating system engineers to take advantage of PCM as main memory and storage by reducing I/O overheads and speeding up both the initialization and termination of program executions. The experimental results show that the performance of PCM as both main memory and storage can be significantly improved with reasonable lifetime, while the system overhead is very limited under coarse-grained wear leveling.

关键词： operating systems (computers) phase change memories program verification storage management I/O overheads PCM storage space PCM translation layer coarse-grained wear leveling integrated memory management integrated storage management joint management scheme operating system operating system implementations phase change memory program executions hardware Joints Memory management Operating systems Performance evaluation Phase change materials Random access memory Store management Operating systems Phase change memory main memory Pulse code modulation PROGRAM EXECUTION random access machine program verification Phase change materials Computer hardware Joints Joints Performance Evaluation

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