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Flattening-based Mapping of Imperfect Loop Nests for CGRAs 14

Flattening-based Mapping of Imperfect Loop Nests for CGRAs

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Lee, Jongeun Seo, Seongseok Lee, Hongsik Sim, Hyeon Uk UNIST Sch ECE Ulsan South Korea

ISBN: (纸本)9781450330510

For loop accelerators such as coarse-grained reconfigurable architectures (CGRAs) and GP-GPUs, nested loops represent an important source of parallelism. Existing solutions to mapping nested loops on CGRAs, however, are either designed for perfectly nested loops only, or expensive and inflexible. Efficient CGRA mapping of imperfect loops with arbitrary nesting depth still remains a challenge. In this paper we propose a compiler-hardware co-operative approach that is flexible and yet able to generate efficient mappings for imperfect nested loops. It is based on loop flattening, but to mitigate the negative impact of flattening we combine loop fission and a light-weight architecture extension that is designed to accelerate common operation patterns appearing frequently in flattened loops. Our experimental results using imperfect loops from multimedia and DSP domains demonstrate that our special operations can cover a large portion of nested loop operations, improve performance of nested loops by nearly 30% over using loop flattening only, and achieve near-ideal executions on CGRAs for imperfect loops.

关键词： parallel processing program compilers program control structures CGRA DSP domains GP-GPUs coarse-grained reconfigurable architectures compiler-hardware cooperative approach flattening-based loop nest mapping light-weight architecture extension loop accelerators loop fission loop flattening multimedia domains nested loop mapping parallelism source Arrays Kernel Nickel Pipeline processing Registers Coarse-grained Reconfigurable Architecture Loops program control structures Imperfect Pipeline processing compilers Registers PARALLEL PROCESSING (COMPUTERS) Nickel Contraceptive Coil FLATTENING Kernel MAPPING(MATHEMATICAL)

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Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded system Design and Optimization 14

Towards Scalable Symbolic Routing for Multi-Objective Networ...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Graf, Sebastian Reimann, Felix Glass, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9781450330510

Symbolic encoding for resource allocation, task binding, and message routing during multi-objective design space exploration (DSE) has gained significant attention in recent years. To determine the message routing, existing symbolic approaches typically rely on an explicit encoding of routing hops which results in a huge number of required variables and/or constraints. As a result, these approaches fail in case of large network diameters and/or a huge number of messages or resources and even for smaller problems, the convergence of the involved optimization process suffers. To tackle this shortcomings, this work proposes three novel symbolic routing encoding strategies that all avoid to encode hops explicitly, but are based on an encoding of individual links or complete sender-receiver paths, but still cover the same design space. The result is a more compact problem representation with less constraints and, in particular, less variables;the latter eliminates ineffective degrees of freedom from the search space and significantly enhances the optimization quality of a multi-objective optimization with even non-linear objectives. In an extensive test-suite, three major classes of wired networked embedded systems are considered: (a) hierarchical stars as in MPSoCs or automotive, (b) redundant backbone buses as common in rail systems or avionics, and (c) mesh-based architectures that often occur in NoC-based MPSoCs. For all three classes, the proposed approaches significantly outperform existing techniques in both scalability and optimization quality and, thus, considerably enlarge the field of application of a multi-objective DSE for the networked embedded system design.

关键词： Embedded systems Encoding Optimization Receivers Resource management Routing Scalability Network routing Scalability Embedded systems embedded system design management of resources Receivers coding

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An Efficient Technique for Computing Importance Measures in Automatic Design of Dependable Embedded systems 14

An Efficient Technique for Computing Importance Measures in ...

引用

international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Aliee, Hananeh Glass, Michael Khosravi, Faramarz Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9781450330510

Importance measure analysis judges the relative importance of components in a system and reveals how each component contributes to the system reliability. In the design of large and complex systems, importance measure analysis can therefore be employed to guide an optimization tool which design decisions to investigate to gain higher reliability. While previous research has mainly concentrated on developing analytical importance measure techniques, the automatic and frequent computing of importance measures as required in the context of design space exploration has got very few, if any attention. This paper presents a highly efficient technique to compute the reliability and structural importance measures of components of a system. The proposed technique considers the reliability of a system implementation and subsequently analyzes the importance measures of its components based on a state-of-the-art Monte Carlo simulation. The technique can therefore estimate the importance measures of all components concurrently, highly improving the performance of the computation compared, e.g., to the well-known Birnbaum approach by the factor of 2n with n being the number of components. Moreover, we show how this algorithm can be extended to support importance measure analysis in the existence of transient faults which is essential since in future systems, transient faults are expected to cause relatively more failures than permanent faults. We integrated the proposed analysis approach in an existing multi-objective local-search algorithm that is part of an automatic system-level design space exploration which seeks for system implementations with highest reliability at lowest possible cost. Experimental results show that the proposed algorithm performs efficiently with negligible imprecision, even for large real world examples.

关键词： importance sampling search problems Birnbaum approach Monte Carlo simulation automatic design automatic system-level design space exploration complex system dependable embedded systems importance measure analysis importance measure techniques large system multiobjective local-search algorithm optimization tool permanent fault structural importance measures system implementation system reliability transient fault Algorithm design and analysis Boolean functions hardware Reliability engineering Space exploration Transient analysis Computer-Aided Design transient fault system implementation permanent fault Space Exploration Algorithm design and analysis Reliability engineering tabu search Complex systems Transient analysis Boolean functions importance sampling Monte Carlo technique Computer hardware

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HYPNOS: An Ultra-Low Power Sleep Mode with SRAM Data Retention for Embedded Microcontrollers 14

HYPNOS: An Ultra-Low Power Sleep Mode with SRAM Data Retenti...

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international conference on hardware / software codesign and system synthesis (CODES+ISSS)

作者： Jayakumar, Hrishikesh Raha, Arnab Raghunathan, Vijay Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781450330510

In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low power (sleep) state when idle, and preserving application state either by retaining the data in-situ in SRAM, or by checkpointing it to FLASH. However, both these approaches have notable drawbacks. In-situ data retention requires the SRAM to remain powered in sleep mode, while checkpointing to FLASH involves significant energy and time overheads. This paper proposes a new ultra-low power sleep mode for micro controllers that overcomes the limitations of both these approaches. Our technique, HYPNOS, is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10x lower) than the typical operating voltage of the microcontroller. HYPNOS exploits this observation by performing extreme voltage scaling when the microcontroller is in sleep mode. We implement and evaluate HYPNOS for the TI MSP430G2452 microcontroller and show that the MCU draws only 26nA in the proposed sleep mode, which is 4x lower than any existing sleep mode that preserves SRAM contents. Further, we show that a complete wireless sensing system using HYPNOS only depletes battery capacity by 42.6nAh in an hour. By decreasing the average power consumption to such minuscule levels, HYPNOS takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

关键词： SRAM chips checkpointing embedded systems microcontrollers power aware computing power consumption storage management Flash HYPNOS MCU SRAM content preservation SRAM data retention TI MSP430G2452 microcontroller battery capacity battery lifetime embedded microcontrollers energy consumption energy harvesting energy overhead extreme voltage scaling heavily duty-cycled embedded system microcontroller operating voltage onchip SRAM time overhead ultralow power sleep mode wireless sensing system Microcontrollers Phasor measurement units Power demand Registers SRAM cells Switches Microcontrollers checkpointing sleeping mode Static random access storage Power consumption Battery Life power aware computing Battery Capacity Flashing Phasor measurement units Store management Power demand Registers energy harvesting Embedded systems

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An Application-Specific Instruction Set for Accelerating Set-Oriented Database Primitives 14

An Application-Specific Instruction Set for Accelerating Set...

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acm SIGMOD international conference on Management of Data

作者： Arnold, Oliver Haas, Sebastian Fettweis, Gerhard Schlegel, Benjamin Kissinger, Thomas Lehner, Wolfgang Tech Univ Dresden Vodafone Chair Mobile Commun Syst Dresden Germany Tech Univ Dresden Database Technol Grp Dresden Germany Oracle Labs Belmont CA USA

ISBN: (纸本)9781450323765

The key task of database systems is to efficiently manage large amounts of data. A high query throughput and a low query latency are essential for the success of a database system. Lately, research focused on exploiting hardware features like superscalar execution units, SIMD, or multiple cores to speed up processing. Apart from these software optimizations for given hardware, even tailor-made processing circuits running on FPGAs are built to run mostly stateless query plans with incredibly high throughput. A similar idea, which was already considered three decades ago, is to build tailor-made hardware like a database processor. Despite their superior performance, such application-specific processors were not considered to be beneficial because general-purpose processors eventually always caught up so that the high development costs did not pay off. In this paper, we show that the development of a database processor is much more feasible nowadays through the availability of customizable processors. We illustrate exemplarily how to create an instruction set extension for set-oriented database primitives. The resulting application-specific processor provides not only a high performance but it also enables very energy-efficient processing. Our processor requires in various configurations more than 960x less energy than a high-end x86 processor while providing the same performance.

关键词： hardware/software-codesign Customizable Processors Instruction Set Extensions

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Context-Sensitive Timing Simulation of Binary Embedded software

Context-Sensitive Timing Simulation of Binary Embedded Softw...

引用

international conference on Compilers, Architecture and synthesis for Embedded systems (CASES)

作者： Ottlik, Sebastian Stattelmann, Stefan Viehl, Alexander Rosenstiel, Wolfgang Bringmann, Oliver FZI Res Ctr Informat Technol D-76131 Karlsruhe Germany ABB Corp Res Res Area Software D-68526 Ladenburg Germany Univ Tubingen D-72076 Tubingen Germany

ISBN: (纸本)9781450330503

We present an approach to accurately simulate the temporal behavior of binary embedded software based on timing data generated using static analysis. As the timing of an instruction sequence is significantly influenced by the microarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional simulation.

关键词： software Timing Simulation Binary Level Simulation Instruction Set Simulation system Level Design Virtual Prototyping

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Formal verification of systemC designs using the BLAST software model checker 7

Formal verification of SystemC designs using the BLAST softw...

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7th international Workshop on Model-Based Architecting and Construction of Embedded systems, ACES-MB 2014, Co-located with acm/IEEE 17th international conference on Model Driven Engineering Languages and systems, MoDELS 2014

作者： Herber, Paula Hünnemeyer, Bettina Technische Universität Berlin Ernst-Reuter-Platz 7 Berlin10587 Germany

systemC is widely used in hardware/software codesign. Although it is also used for the design of safety-critical applications, existing formal verification techniques for systemC are still hardly used in industrial practice. The main reasons for this are scalability issues, the lacking support for many practically relevant systemC language constructs, and that counter-examples are not always easy to use for debugging. In this paper, we present an approach for the formal verification of systemC designs using the BLAST model checker. The main advantages of our approach are: First, we enable a fully automatic verification of systemC designs that makes use of counter-example guided abstraction refinement. Second, we support a large subset of systemC, including pointers, arrays, and structs. Third, we ease debugging by keeping the structure of the design transparent to the designer. We demonstrate the applicability of our approach with experimental results from an Anti-Slip Regulation and Anti-Lock Braking system.

关键词： Formal verification

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Dark silicon as a challenge for hardware/software co-design

Dark silicon as a challenge for hardware/software co-design

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Muhammad Shafique Siddharth Garg Tulika Mitra Sri Parameswaran Jörg Henkel Chair for Embedded Systems (CES) Karlsruhe Institute of Technology Germany Department of ECE University of Waterloo Canada University of New South Wales Sydney NSW AU

Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to stay within the power budget and safe thermal limits, while the other resources will have to be kept powered-off or “dark”. In other words, chips will have an abundance of transistors, i.e., more than the number that can be simultaneously powered-on. Heterogeneous computing has been proposed as one way to effectively leverage this abundance of transistors in order to increase performance, energy efficiency and even reliability within power and thermal constraints. However, several critical challenges remain to be addressed including design, automated synthesis, design space exploration and run-time management of heterogeneous dark silicon processors. The hardware/software co-design and synthesis community has potentially much to contribute in solving these new challenges introduced by dark silicon and, in particular, heterogeneous computing. In this paper, we identify and highlight some of these critical challenges, and outline some of our early research efforts in addressing them.

关键词： Silicon Program processors Reliability Computer architecture Switches hardware

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MEMOCODE 2014 design contest: k-Nearest Neighbors with Mahalanobis distance metric

MEMOCODE 2014 design contest: k-Nearest Neighbors with Mahal...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Peter Milder Department of Electrical and Computer Engineering Stony Brook University Stony Brook NY

The MEMOCODE 2014 hardware/software codesign contest problem is k-Nearest Neighbor search using the Mahalanobis distance metric. Given a data set of points in multi-dimensional space, the goal is to find the k points that are nearest to any given point in that space (quantified with the given distance metric). Contestants were given one month to develop a system to perform the kNN search, aiming to maximize performance or cost-adjusted performance. The two winning teams, which have been invited to contribute papers describing their techniques, combined algorithmic and implementation optimizations. The pure-performance winners targeted the Convey HC-2ex hybrid FPGA/multicore system, while the winners for cost-adjusted performance targeted an Intel multicore.

关键词： Runtime Measurement software Field programmable gate arrays Covariance matrices conferences hardware

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Effective platform-level exploration for heterogeneous multicores exploiting simulation-induced slacks 14

Effective platform-level exploration for heterogeneous multi...

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5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2014

作者： Sotiriou-Xanthopoulos, Efstathios Xydis, Sotirios Siozios, Kostas Economakos, George Soudris, Dimitrios Athens Greece

ISBN: (纸本)9781450326070

Heterogeneous Multi-Processor systems-on-Chip (MPSoC) exhibit increased design complexity due to numerous architectural parameters and hardware/software partitioning schemes. Automated Design Space Exploration (DSE) becomes an essential design procedure to discover optimized solutions in a reasonable time. For high-quality DSE, the accurate solution evaluation is a strong requirement. To this direction, High-Level synthesis (HLS) can be used for the characterization of the design solutions. In this paper, we propose (a) a platform design methodology that exploits simulation-induced slacks generated by avoiding simulation re-initializations and exploits the gained time for HLS, and (b) a DSE tool-flow which takes into account multiple HW/SW partitioning schemes and intelligently schedules system evaluations. Experimental results show that the proposed methodology achieves 17% simulation improvements together with 77% higher accuracy, in comparison to a typical exploration approach. Copyright © 2014 acm.

关键词： High level synthesis

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