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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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From visual to logical formalisms for SoC validation

From visual to logical formalisms for SoC validation

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Ranan Fraer Doron Keren Zurab Khasidashvili Alexander Novakovsky Avi Puder Eli Singerman Eran Talmor Moshe Y. Vardi Jin Yang Design Technology and Solutions Intel Corporation Haifa Israel Dept. of Computer Science Rice University Houston Texas

In current SoCs, key infrastructure capabilities are distributed across many components and involve tight software, firmware, and hardware interaction. Examples include resets, power management, security, and more. The architectural complexity of these features often results in specification errors that when found quite late in the product life cycle are very costly to fix. This means that we have to find ways to analyze the architectural specification and not only the implementation. To address these issues, we describe a framework called iPave that supports the following capabilities: (1) A common, formal system-level specification serving as a contract between different design teams; (2) Specification analysis with focus on cross-component assumptions and dependencies; and (3) A method to reuse the specification as a global checker to assure that the implementation is compliant with the specification across all validation platforms (simulation, emulation, silicon). At the front end of this framework we have an intuitive visual formalism, iFlow, which makes it easy for architects to specify system-level protocols, while at the back end we have a new logical formalism, called Logic Sequence Diagrams (LSDs), which enables formal compliance checking across different validation platforms.

关键词： Protocols Visualization hardware software Semantics system-on-chip Computer architecture

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Embedded systems Week 2008 - Proceedings of the 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM...

引用

Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

ISBN: (纸本)9781605584706

The proceedings contain 46 papers. The topics discussed include: concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design;a time-predictable system initialization design for huge-capacity flash-memory storage systems;deterministic service guarantees for NAND flash using partial block cleaning;static analysis of processor stall cycle aggregation;application specific non-volatile primary memory for embedded systems;scratchpad allocation for concurrent embedded software;hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits;a performance-oriented hardware/software partitioning for datapath applications;traversal caches: a first step towards FPGA acceleration of pointer-based data structures;and distributed and low-power synchronization architecture for embedded multiprocessors.

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Dark silicon as a challenge for hardware/software co-design: invited special session paper 14

Dark silicon as a challenge for hardware/software co-design:...

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Proceedings of the 2014 international conference on hardware/software codesign and system synthesis

作者： Muhammad Shafique Siddharth Garg Tulika Mitra Sri Parameswaran Jörg Henkel Karlsruhe Institute of Technology Germany University of Waterloo Canada National University of Singapore Singapore University of New South Wales Australia

ISBN: (纸本)9781450330510

Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so on) in order to stay within the power budget and safe thermal limits, while the other resources will have to be kept powered-off or "dark". In other words, chips will have an abundance of transistors, i.e., more than the number that can be simultaneously powered-on. Heterogeneous computing has been proposed as one way to effectively leverage this abundance of transistors in order to increase performance, energy efficiency and even reliability within power and thermal constraints. However, several critical challenges remain to be addressed including design, automated synthesis, design space exploration and run-time management of heterogeneous dark silicon processors. The hardware/software co-design and synthesis community has potentially much to contribute in solving these new challenges introduced by dark silicon and, in particular, heterogeneous computing. In this paper, we identify and highlight some of these critical challenges, and outline some of our early research efforts in addressing them.

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An Equivalence Checker for hardware-Dependent Embedded system software

An Equivalence Checker for Hardware-Dependent Embedded Syste...

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11th IEEE/acm international conference on Formal Methods and Models for codesign (MEMOCODE)

作者： Villarraga, Carlos Schmidt, Bernard Bormann, Joerg Bartsch, Christian Stoffel, Dominik Kunz, Wolfgang U Kaiserslautern Dept Elect & Comp Eng Kaiserslautern Germany

ISBN: (纸本)9781479909032

This paper presents a novel approach to formally prove the equivalence of low-level hardware-dependent programs. Inspired by hardware verification techniques, a software miter is created that compares the behaviors of two programs, taking into account the interfaces between the software and the hardware environments. Two programs are considered equivalent if they produce the same outputs for the same input assignments and also exhibit the same sequences of interactions with the relevant hardware peripherals. This motivates a hardware-dependent computational model combining a path-oriented program view, as is common in hardware-independent software verification, with a structural hardware representation of the program's computation. Experimental results show the effectiveness of the proposed technique for industrial low-level software in important equivalence checking scenarios such as code porting and automated/manual code transformations.

关键词： Cosine transforms

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hardware neural network accelerators

Hardware neural network accelerators

引用

11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Temam, O. INRIA Saclay France

""Because of increasingly stringent energy constraints (e.g., Dark Silicon, there is a growing consensus in the community that we may be moving towards heterogeneous multi-core architectures, composed of a m... 详细信息

ISBN: (纸本)9781479914173

关键词： application specific integrated circuits fault tolerant computing graphics processing units learning (artificial intelligence) multiprocessing systems neural nets parallel architectures power aware computing

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MEMOCODE 2013 hardware/software Co-design Contest: Stereo Matching

MEMOCODE 2013 Hardware/Software Co-design Contest: Stereo Ma...

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11th IEEE/acm international conference on Formal Methods and Models for codesign (MEMOCODE)

作者： Nurvitadhi, Eriko Intel Sci & Technol Ctr Embedded Comp Pittsburgh PA 15213 USA

ISBN: (纸本)9781479909032

The MEMOCODE 2013 design contest problem is matching. Given a stereo image pair (i. e., a left image and right image), the challenge is to infer the depth information e., third dimension) for each pixel in the image utilizing belief algorithm. Contestants were given a month to a fast and/or cost-effective system for stereo matching. a total of eight participating teams, three winners were based on pure-performance and cost-adjustedmetrics, taking into consideration inference achieved by their design solutions. The winning teams hierarchical belief propagation algorithm on Intel multisystems, streaming tree-reweighted message passing (TRWalgorithm on Convey HC-1 FPGA platform, and tile-based propagation algorithm on Nvidia GTX 680 GPU platform.

关键词： stereo matching belief propagation hardware-software codesign multicore FPGAs GPUs

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system level synthesis of hardware for DSP applications using pre-characterized function implementations

System level synthesis of hardware for DSP applications usin...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Li, Shuo Farahini, Nasim Hemani, Ahmed Rosvall, Kathrin Sander, Ingo ES/ICT/KTH Forum 120 SE-164 40 Kista Sweden

ISBN: (纸本)9781479914173

SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results. © 2013 IEEE.

关键词： Data transfer

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APECS: An AADL and Polychrony based Embedded Computing system Design Environment with an Elevator Control Case Study

APECS: An AADL and Polychrony based Embedded Computing Syste...

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11th IEEE/acm international conference on Formal Methods and Models for codesign (MEMOCODE)

作者： Anderson, Matthew Shukla, Sandeep K. Virginia Polytech Inst & State Univ Bradley Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)9781479909032

Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for capturing an entire distributed platform architecture (hardware components, protocols, and software architecture annotated with properties including real-time measures). The software architecture captures the location and structure of processes, threads, and the data and control flow specifications. The behavior of the processes/threads/subprograms are provided via a native state machine language or via a behavioral annex. Schedulability, performance, and other system level properties can be analyzed using various tools. Even code synthesis - targeting the formally described platform components and middleware can be enabled if the threads/processes can be behaviorally specified. In this paper, we describe our methodology and a design environment both named APECS. APECS is meant for enabling an end-to-end distributed real-time embedded system design which integrates a number of existing tools, and our own polychronous language based specification language MRICDF, and the corresponding synthesis methodology. While the environment is in an advanced stage of development, we illustrate the architecture of the design environment, and illustrate the methodology through a non-trivial case study. The case study uses APECS methodology and tools in developing the distributed control for a 4 bank elevator system in a 5 story building. We posit this paper as a methodology and tool paper and it is written in a tutorial spirit rather than a paper describing new theories or algorithms.

关键词： software architecture designing of environment avionics Developmental stages elevator control Environments embedded system design Building construction ARCHITECTURE Embedded computing Case studies paper methodology Middleware Language

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Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis

Bound-oriented parallel pruning approaches for efficient res...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Chen, Mingsong Zhou, Lei Pu, Geguang He, Jifeng Shanghai Key Laboratory of Trustworthy Computing East China Normal Univeristy China

ISBN: (纸本)9781479914173

As a key step of high-level synthesis (HLS), resource constrained scheduling (RCS) tries to find an optimal schedule which can dispatch all the operations with minimum latency under specific resource constraints. Branch-and-bound heuristics are promising to achieve such an optimal schedule quickly, since they can prune away large parts of infeasible solution space during the exploration. However, few of them are based on the prevalent multi-core platforms. Based on the bound information, this paper exploits the parallel pruning potentials from different perspectives and proposes various efficient techniques that can substantially reduce the overall RCS search efforts. The experimental results demonstrate that our approach can reduce the RCS time drastically. © 2013 IEEE.

关键词： High level synthesis

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Automatic refinement of requirements for verification throughout the SoC design flow

Automatic refinement of requirements for verification throug...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Pierre, Laurence Bel Hadj Amor, Zeineb TIMA Laboratory CNRS-INPG-UJF 46 Avenue Félix Viallet 38031 Grenoble cedex France

ISBN: (纸本)9781479914173

This paper focuses on the verification of requirements for hardware/software systems on chip (SoC's) along the design flow. In the early stages of this flow, the Electronic system Level (ESL) description style, and languages such as systemC TLM, enable high-level debugging of the SoC functionality. In the last stages, hardware blocks become RTL or gate level (VHDL or Verilog) descriptions. We have developed two autonomous Assertion-Based Verification (ABV) solutions, for systemC TLM platforms and for VHDL/Verilog IP blocks: designs are automatically instrumented with ad hoc property checkers produced from requirements formalized as PSL assertions. Furthermore, for a comprehensive and seamless verification flow, analogous requirements should be verifiable before and after ESL-to-RTL hardware refinement. This requires the transformation of ESL assertions into their counterparts at the RT level. This paper discusses this issue and proposes a first set of transformation rules for the automatic refinement of PSL assertions from the system level to the signal level. Properties of an industrial case study are used as illustrative examples. © 2013 IEEE.

关键词： system-on-chip

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