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synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

Synthesis-friendly techniques for tightly-coupled integratio...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Conti, Francesco Marongiu, Andrea Benini, Luca DEI Università di Bologna Italy

ISBN: (纸本)9781479914173

Several many-core designs tackle scalability issues by leveraging tightly-coupled clusters as building blocks, where low-latency, high-bandwidth interconnection between a small/medium number of cores and L1 memory achieves high performance/watt. Tight coupling of hardware accelerators into these multicore clusters constitutes a promising approach to further improve performance/area/watt. However, accelerators are often clocked at a lower frequency than processor clusters for energy efficiency reasons. In this paper, we propose a technique to integrate shared-memory accelerators within the tightly-coupled clusters of the STMicroelectronics STHORM architecture. Our methodology significantly relaxes timing constraints for tightly-coupled accelerators, while optimizing data bandwidth. In addition, our technique allows to operate the accelerator at an integer submultiple of the cluster frequency. Experimental results show that the proposed approach allows to recover up to 84% of the slow-down implied by reduced accelerator speed. © 2013 IEEE.

关键词： Energy efficiency

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A cyber-physical system approach to artificial pancreas design

A cyber-physical system approach to artificial pancreas desi...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Ghorbani, Mahboobeh Bogdan, Paul University of Southern California Los Angeles CA United States

ISBN: (纸本)9781479914173

Healthcare costs in the US are among the highest in the world. Widespread chronic diseases such as diabetes constitute a significant cause of rising healthcare costs. Despite the increased need for smart healthcare systems that monitor patients' body balance, there is no coherent theory that facilitates the design and optimization of efficient and robust cyber physical systems. In this paper, we propose a mathematical model for capturing the dynamics of blood glucose characteristics (e.g., time dependent fractal behavior) observed in real world measurements via fractional calculus concepts. Building on our time dependent fractal model, we propose a novel mathematical model as well as hardware architecture for an artificial pancreas that relies on solving a constrained multi-fractal optimal control problem for regulating insulin injection. We verify the accuracy of our mathematical model by comparing it to conventional nonfractal models using real world measurements and showing that the nonlinear optimal controller based on fractal calculus concepts is superior to nonfractal controllers. We also verified the feasibility of in silico realization of the proposed optimal control algorithm by prototyping on FPGA platform. © 2013 IEEE.

关键词： Real time systems

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On the automatic generation of GPU-oriented software applications from RTL IPs

On the automatic generation of GPU-oriented software applica...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Bombieri, Nicola Fummi, Franco Vinco, Sara Dipartimento di Informatica Università di Verona Italy

ISBN: (纸本)9781479914173

Graphics processing units (GPUs) have been explored as a new computing paradigm for accelerating computation intensive applications. In particular, the combination between GPUs and CPU has proved to be an effective solution for accelerating the software execution, by mixing the few CPU cores optimized for serial processing with many smaller GPU cores designed for massively parallel computations. In addition, sustained by the need of low power consumption besides high performance, a recent trend is combining GPUs and CPU onto a single die (e.g., AMD Fusion, Intel Sandy Bridge, NVIDIA Tegra). The good tradeoff between computing capability and power consumption makes the integrated GPUs a promising alternative for accelerating a wide range of software application for embedded systems. Nevertheless, algorithms must be redesigned to take advantage of these architectures and such a manual parallelization often results in being unsatisfactory. This paper presents a methodology to automatically generate software applications for GPUs, by reusing existing and preverified register-transfer level (RTL) intellectual-properties (IPs). The methodology aims at exploiting the intrinsic parallelism of RTL IPs (such as process concurrency and pipeline micro-architecture) for generating the parallel software implementation of the functionality. The experimental results show how the performance obtained by running the RTL functionality as software applications on GPUs outperform those provided by the RTL code mapped into a hardware accelerator. © 2013 IEEE.

关键词： Graphics processing unit

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CMSM: An efficient and effective code management for software managed multicores

CMSM: An efficient and effective code management for softwar...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Bai, Ke Lu, Jing Shrivastava, Aviral Holton, Bryce Compiler Microarchitecture Laboratory Arizona State University Tempe AZ 85287 United States

ISBN: (纸本)9781479914173

As we scale the number of cores in a multicore processor, scaling the memory hierarchy is a major challenge. software Managed Multicore (SMM) architectures are one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory. If all the code and data of the task mapped to a core do not fit on its local scratchpad memory, then explicit code and data management is required. In this paper, we solve the problem of efficiently managing code on an SMM architecture. We extend the state of the art by: i) correctly calculating the code management overhead, ii) even in the presence of branches in the task, and iii) developing a heuristic CMSM (Code Mapping for software Managed multicores) that results in efficient code management execution on the local scratchpad memory. Our experimental results collected after executing applications from MiBench suite [1] on the Cell SPEs (Cell is an SMM architecture) [2], demonstrate that correct management cost calculation and branch consideration can improve performance by 12%. Our heuristic CMSM can reduce runtime in more than 80% of the cases, and by up to 20% on our set of benchmarks. © 2013 IEEE.

关键词： Embedded systems

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PvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment

PvFPGA: Accessing an FPGA-based hardware accelerator in a pa...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Wang, Wei Bolic, Miodrag Parri, Jonathan Computer Architecture Research Group University of Ottawa Ottawa ON Canada

ISBN: (纸本)9781479914173

In this paper we present pvFPGA, the first system design solution for virtualizing an FPGA-based hardware accelerator on the x86 platform. Our design adopts the Xen virtual machine monitor (VMM) to build a paravirtualized environment, and a Xilinx Virtex-6 as an FPGA accelerator. The accelerator communicates with the x86 server via PCI Express (PCIe). In comparison to the recent accelerator virtualization solutions which primarily intercept and redirect API calls to the hosted or privileged domain's user space, pvFPGA virtualizes an FPGA accelerator directly at the lower device driver level. This gives rise to higher efficiency and lower overhead. In pvFPGA, each unprivileged domain allocates a shared data pool for both user-kernel and inter-domain data transfer. In addition, we propose a new component, the coprovisor, which enables multiple domains to simultaneously access an FPGA accelerator. The experimental results have shown that 1) pvFPGA achieves close-to-zero overhead compared to accessing the FPGA accelerator without the VMM layer, 2) the FPGA accelerator is successfully shared by multiple domains, and 3) distributing different maximum data transfer bandwidths to different domains is achieved by regulating the size of the shared data pool at the split driver loading time. © 2013 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Designing a residential hybrid electrical energy storage system based on the energy buffering strategy

Designing a residential hybrid electrical energy storage sys...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Zhu, Di Yue, Siyu Wang, Yanzhi Kim, Younghyun Chang, Naehyuck Pedram, Massoud University of Southern California CA United States Seoul National University Korea Republic of

ISBN: (纸本)9781479914173

Due to severe variation in load demand over time, utility companies generally raise electrical energy price during periods of high load demand. A grid-connected hybrid electrical energy storage (HEES) system can help residential users lower their electric bills by storing energy during low-price hours and releasing the stored energy during high-price hours. A HEES system consists of different types of electrical energy storage (EES) elements, utilizing the benefits of each type while hiding their weaknesses. This paper presents a residential energy management system to maximize the annual profits on residential electric bills, based on a HEES system comprised of a lead-acid battery bank as the main storage bank and a Li-ion battery bank as the energy buffer. We first derive the optimal daily energy management policy based on energy buffering to minimize the daily energy cost. Next, we find the near-optimal design specifications of the energy management system, aiming at maximizing the amortized annual profits under practical constraints. We show that this system achieves averagely 11.10% more profits compared to the none-buffering HEES system. © 2013 IEEE.

关键词： Energy management

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A reconfigurable real-time SDRAM controller for mixed time-criticality systems

A reconfigurable real-time SDRAM controller for mixed time-c...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Goossens, Sven Kuijsten, Jasper Akesson, Benny Goossens, Kees Eindhoven University of Technology Netherlands

ISBN: (纸本)9781479914173

Verifying real-time requirements of applications is increasingly complex on modern systems-on-Chips (SoCs). More applications are integrated into one system due to power, area and cost constraints. Resource sharing makes their timing behavior interdependent, and as a result the verification complexity increases exponentially with the number of applications. Predictable and composable virtual platforms solve this problem by enabling verification in isolation, but designing SoC resources suitable to host such platforms is challenging. This paper focuses on a reconfigurable SDRAM controller for predictable and composable virtual platforms. The main contributions are: 1) A run-time reconfigurable SDRAM controller architecture, which allows trade-offs between guaranteed bandwidth, response time and power. 2) A methodology for offering composable service to memory clients, by means of composable memory patterns. 3) A reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level systemC model, and in synthesizable VHDL for use on an FPGA. © 2013 IEEE.

关键词： system-on-chip

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VarEMU: An emulation testbed for variability-aware software

VarEMU: An emulation testbed for variability-aware software

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Wanner, Lucas Elmalaki, Salma Lai, Liangzhen Gupta, Puneet Srivastava, Mani University of California Los Angeles CA United States

ISBN: (纸本)9781479914173

Modern integrated circuits, fabricated in nanometer technologies, suffer from significant power/performance variation across-chip, chip-to-chip and over time due to aging and ambient fluctuations. Furthermore, several existing and emerging reliability loss mechanisms have caused increased transient, intermittent and permanent failure rates. While this variability has been typically addressed by process, device and circuit designers, there has been a recent push towards sensing and adapting to variability in the various layers of software. Current hardware platforms, however, typically lack variability sensing capabilities. Even if sensing capabilities were available, evaluating variability-aware software techniques across a significant number of hardware samples would prove exceedingly costly and time consuming. We introduce VarEMU, an extension to the QEMU virtual machine monitor that serves as a framework for the evaluation of variability-aware software techniques. VarEMU provides users with the means to emulate variations in power consumption and in fault characteristics and to sense and adapt to these variations in software. Through the use (and dynamic change) of parameters in a power model, users can create virtual machines that feature both static and dynamic variations in power consumption. Faults may be injected before or after, or completely replace the execution of any instruction. Power consumption and susceptibility to faults are also subject to dynamic change according to an aging model. A software stack for VarEMU features precise control over faults and provides virtual energy monitors to the operating system and processes. This allows users to precisely quantify and evaluate the effects of variations on individual applications. We show how VarEMU tracks energy consumption according to variation-aware power and aging models and give examples of how it may be used to quantify how faults in instruction execution affect applications. © 2013 IEEE.

关键词： Electric power utilization

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Improving polyhedral code generation for high-level synthesis

Improving polyhedral code generation for high-level synthesi...

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11th acm/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Zuo, Wei Li, Peng Chen, Deming Pouchet, Louis-Nöel Zhong, Shunan Cong, Jason Beijing Institute of Technology China Peking University China PKU UCLA Joint Research Institution for Science and Engineering United States University of California Los Angeles CA United States University of Illinois Urbana-Champaign IL United States

ISBN: (纸本)9781479914173

High-level synthesis (HLS) tools are now capable of generating high-quality RTL codes for a number of programs. Nevertheless, for best performance aggressive program transformations are still required to exploit data reuse and enable communication/computation overlap. The polyhedral compilation framework has shown great promise in this area with the development of HLS-specific polyhedral transformation techniques and tools. However, all these techniques rely on polyhedral code generation to translate a schedule for the program's operations into an actual C code that is input to the HLS tool. In this work we study the changes to the state-of-the-art polyhedral code generator CLooG which are required to tailor it for HLS purposes. In particular, we develop various techniques to significantly improve resource utilization on the FPGA. We also develop a complete technique geared towards effective code generation of rectangularly tiled code, leading to further improvements in resource utilization. We demonstrate our techniques on a collection of affine benchmarks, reducing by 2x on average (up to 10x) the area used after high-level synthesis. © 2013 IEEE.

关键词： High level synthesis

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11th acm/IEEE international conference on Formal Methods and Models for codesign, MEMOCODE 2013

11th ACM/IEEE International Conference on Formal Methods and...

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11th acm/IEEE international conference on Formal Methods and Models for codesign, MEMOCODE 2013

ISBN: (纸本)9781479909032

The proceedings contain 20 papers. The topics discussed include: APECS: an AADL and polychrony based embedded computing system design environment and an elevator case study;FERAL - framework for simulator coupling on requirements and architecture level;back to basics: homogeneous representations of synchronous dataflow graphs;automated extraction of scenario sequences from disciplined dataflow networks;causal analysis of probabilistic counterexamples;synthesizing distributed scheduling implementation for probabilistic component-based systems;symbolic software model validation;equivalence checking for synchronous elastic circuits;an equivalence checker for hardware-dependent embedded system software;MEMOCODE 2013 hardware/software co-design contest: stereo matching;fast and adaptive BP-based multi-core implementation for stereo matching;FPGA acceleration of Markov random field TRW-S inference for stereo;and compiler-directed memory hierarchy design for low-energy embedded systems.

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