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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是341-350 订阅

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SDC-Based Modulo Scheduling for Pipeline synthesis 13

SDC-Based Modulo Scheduling for Pipeline Synthesis

引用

32nd IEEE/acm international conference on Computer-Aided Design (ICCAD)

作者： Zhang, Zhiru Liu, Bin Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA Micron Technol Inc San Jose CA USA

ISBN: (纸本)9781479910717

Modulo scheduling is a popular technique to enable pipelined execution of successive loop iterations for performance improvement. While a variety of modulo scheduling algorithms exist for software pipelining, they are not amenable to many complex design constraints and optimization goals that arise in the hardware synthesis context. In this paper we describe a modulo scheduling framework based on the formulation of system of difference constraints (SDC). Our framework can systematically model a rich set of performance constraints that are specific to the hardware design. The scheduler also exploits the unique mathematical properties of SDC to carry out efficient global optimization and fast incremental update on the constraint system to minimize the resource usage of the synthesized pipeline. Experiments demonstrate that our proposed technique provides efficient solutions for a set of real-life applications and compares favorably against a widely used lifetime-sensitive modulo scheduling algorithm.

关键词： high level synthesis pipeline processing scheduling

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From software to accelerators with LegUp high-level synthesis

From software to accelerators with LegUp high-level synthesi...

引用

2013 international conference on Compilers, Architecture and synthesis for Embedded systems, CASES 2013

作者： Canis, Andrew Choi, Jongsok Fort, Blair Lian, Ruolong Huang, Qijing Calagar, Nazanin Gort, Marcel Qin, Jia Jun Aldham, Mark Czajkowski, Tomasz Brown, Stephen Anderson, Jason ECE Department University of Toronto Toronto ON Canada

ISBN: (纸本)9781479914005

Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support. © 2013 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Tutorials

Tutorials

引用

international conference on hardware/software codesign and system synthesis (CODES)

Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.

关键词： Embedded systems Program processors Unified modeling language Computer architecture hardware Reliability

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A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters 13

A variability-aware OpenMP environment for efficient executi...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Abbas Rahimi Andrea Marongiu Rajesh K. Gupta Luca Benini Department of Computer Science and Engineering UC San Diego La Jolla CA USA Dipartimento di Ingegneria dell'Energia Elettrica e dell'lnformazione Universita di Bologna Bologna Italy

ISBN: (纸本)9781479914173

We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floating-point units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, our programming and runtime environment also supports controlled approximate computation through a combination of design-time and runtime techniques. We provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately. We use a profiling technique to identify tolerable error significance and error rate thresholds in error-tolerant image processing applications. This information guides an application-driven hardware FPU synthesis and optimization design flow to generate efficient FPUs. At runtime, the scheduler utilizes FPV metadata and promotes FPUs to accurate mode, or demotes them to approximate mode depending upon the code region requirements. We demonstrate the effectiveness of our approach (in terms of energy savings) on a 16-core tightly-coupled cluster with eight shared-FPUs for both error-tolerant and general-purpose error-intolerant applications.

关键词： Pipelines Timing Approximation methods Registers Computer architecture Runtime software

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Designing a residential hybrid electrical energy storage system based on the energy buffering strategy 13

Designing a residential hybrid electrical energy storage sys...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Di Zhu Siyu Yue Yanzhi Wang Younghyun Kim Naehyuck Chang Massoud Pedram University of Southern California CA USA Seoul National University Korea

ISBN: (纸本)9781479914173

Due to severe variation in load demand over time, utility companies generally raise electrical energy price during periods of high load demand. A grid-connected hybrid electrical energy storage (HEES) system can help residential users lower their electric bills by storing energy during low-price hours and releasing the stored energy during high-price hours. A HEES system consists of different types of electrical energy storage (EES) elements, utilizing the benefits of each type while hiding their weaknesses. This paper presents a residential energy management system to maximize the annual profits on residential electric bills, based on a HEES system comprised of a lead-acid battery bank as the main storage bank and a Li-ion battery bank as the energy buffer. We first derive the optimal daily energy management policy based on energy buffering to minimize the daily energy cost. Next, we find the near-optimal design specifications of the energy management system, aiming at maximizing the amortized annual profits under practical constraints. We show that this system achieves averagely 11.10% more profits compared to the none-buffering HEES system.

关键词： Batteries Lead Discharges (electric) Pricing Energy management Supercapacitors

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An Equivalence Checker for hardware-Dependent Embedded system software

An Equivalence Checker for Hardware-Dependent Embedded Syste...

引用

IEEE/acm international conference on Formal Methods and Models for codesign

作者： Carlos Villarraga Bernard Schmidt Jorg Bormann Christian Bartsch Dominik Stoffel Wolfgang Kunz Dept. of Electrical and Computer Eng. U. of Kaiserslautern

ISBN: (纸本)9781479909049

This paper presents a novel approach to formally prove the equivalence of low-level hardware-dependent programs. Inspired by hardware verification techniques, a software miter is created that compares the behaviors of two programs, taking into account the interfaces between the software and the hardware environments. Two programs are considered equivalent if they produce the same outputs for the same input assignments and also exhibit the same sequences of interactions with the relevant hardware peripherals. This motivates a hardware-dependent computational model combining a path-oriented program view, as is common in hardware-independent software verification, with a structural hardware representation of the program's computation. Experimental results show the effectiveness of the proposed technique for industrial low-level software in important equivalence checking scenarios such as code porting and automated/manual code transformations.

关键词： equivalence program verification computer software checker Computer hardware transcoding hardware level LOW LEVEL computer programs Equivalent

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hardware neural network accelerators 13

Hardware neural network accelerators

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： O. Temam INRIA Saclay France

ISBN: (纸本)9781479914173

Because of increasingly stringent energy constraints (e.g., Dark Silicon, there is a growing consensus in the community that we may be moving towards heterogeneous multi-core architectures, composed of a mix of cores and accelerators. Because our community is traditionally focused on general-purpose computing, we have been especially considering accelerator approaches such as GPUs and reconfigurable circuits. An attractive alternative is to investigate accelerators which are focused on a few key algorithms: key algorithms still mean broad application scope, but few algorithms enable energy efficient and cost-effective accelerators.

关键词： Artificial neural networks hardware Computer architecture Circuit faults Biological neural networks Communities

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WHISK: An uncore architecture for Dynamic Information Flow Tracking in heterogeneous embedded SoCs 13

WHISK: An uncore architecture for Dynamic Information Flow T...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Joël Porquet Simha Sethumadhavan Department of Computer Science Columbia University NY

ISBN: (纸本)9781479914173

In this paper, we describe for the first time, how Dynamic Information Flow Tracking (DIFT) can be implemented for heterogeneous designs that contain one or more on-chip accelerators attached to a network-on-chip. We observe that implementing DIFT for such systems requires holistic platform level view, i.e., designing individual components in the heterogeneous system to be capable of supporting DIFT is necessary but not sufficient to correctly implement full-system DIFT. Based on this observation we present a new system architecture for implementing DIFT, and also describe wrappers that provide DIFT functionality for third-party IP components. Results show that our implementation minimally impacts performance of programs that do not utilize DIFT, and the price of security is constant for modest amounts of tagging and then sub-linearly increases with the amount of tagging.

关键词： Tagging system-on-chip Computer architecture Security hardware software Engines

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system level synthesis of hardware for DSP applications using pre-characterized function implementations 13

System level synthesis of hardware for DSP applications usin...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Shuo Li Nasim Farahini Ahmed Hemani Kathrin Rosvall Ingo Sander Royal Institute of Technology (KTH) Kista Sweden

ISBN: (纸本)9781479914173

SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results.

关键词： Libraries Abstracts Field programmable gate arrays

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Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis 13

Bound-oriented parallel pruning approaches for efficient res...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mingsong Chen Lei Zhou Geguang Pu Jifeng He Shanghai Key Laboratory of Trustworthy Computing East China Normal Univeristy Shanghai China

ISBN: (纸本)9781479914173

As a key step of high-level synthesis (HLS), resource constrained scheduling (RCS) tries to find an optimal schedule which can dispatch all the operations with minimum latency under specific resource constraints. Branch-and-bound heuristics are promising to achieve such an optimal schedule quickly, since they can prune away large parts of infeasible solution space during the exploration. However, few of them are based on the prevalent multi-core platforms. Based on the bound information, this paper exploits the parallel pruning potentials from different perspectives and proposes various efficient techniques that can substantially reduce the overall RCS search efforts. The experimental results demonstrate that our approach can reduce the RCS time drastically.

关键词： Optimal scheduling Schedules Estimation Job shop scheduling Processor scheduling Delays

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