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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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Improving polyhedral code generation for high-level synthesis 13

Improving polyhedral code generation for high-level synthesi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wei Zuo Peng Li Deming Chen Louis-Noël Pouchet Shunan Zhong Jason Cong Beijing Institute of Technology PKU/UCLA Joint Research Institution for Science and Engineering University of Illinois at Urbana-Champaign University of California Los Angeles

ISBN: (纸本)9781479914173

High-level synthesis (HLS) tools are now capable of generating high-quality RTL codes for a number of programs. Nevertheless, for best performance aggressive program transformations are still required to exploit data reuse and enable communication/computation overlap. The polyhedral compilation framework has shown great promise in this area with the development of HLS-specific polyhedral transformation techniques and tools. However, all these techniques rely on polyhedral code generation to translate a schedule for the program's operations into an actual C code that is input to the HLS tool. In this work we study the changes to the state-of-the-art polyhedral code generator CLooG which are required to tailor it for HLS purposes. In particular, we develop various techniques to significantly improve resource utilization on the FPGA. We also develop a complete technique geared towards effective code generation of rectangularly tiled code, leading to further improvements in resource utilization. We demonstrate our techniques on a collection of affine benchmarks, reducing by 2x on average (up to 10x) the area used after high-level synthesis.

关键词： Field programmable gate arrays Optimization Tiles Benchmark testing Table lookup Digital signal processing Measurement

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Dimensioning and configuration of EES systems for electric vehicles with boundary-conditioned adaptive scalarization 13

Dimensioning and configuration of EES systems for electric v...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wanli Chang Martin Lukasiewycz Sebastian Steinhorst Samarjit Chakraborty TUM CREATE Singapore TU Munich Germany

ISBN: (纸本)9781479914173

Electric vehicles (EVs) are widely considered as a solution for efficient, sustainable and intelligent transportation. An electrical energy storage (EES) system is the most important component in an EV in terms of performances and cost. This work proposes an approach for optimal dimensioning and configuration of EES systems in EVs. It is challenging to find optimal design points in the parameter space, which expands exponentially with the number of battery types available and the number of cells that can be implemented for each type. A multi-objective optimization problem is formulated with the driving range, rated power output, installation space and cost as design targets. We report a novel boundary-conditioned adaptive scalarization technique to solve both convex and concave problems. It provides a Pareto surface of evenly distributed Pareto points, presents the group of Pareto points according to different specific requirements from automotive manufacturers and also takes the fact in EES system design into account that the importance of an objective could be nonlinear to its value. Numerical and practical experiments prove that our proposed approach is effective for industry use and produces optimal solutions.

关键词： Batteries Optimization Mathematical model Vehicles Equations Linear programming system analysis and design

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pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment 13

pvFPGA: Accessing an FPGA-based hardware accelerator in a pa...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Wei Wang Miodrag Bolic Jonathan Parri Computer Architecture Research Group University of Ottawa Ottawa Ontario Canada

ISBN: (纸本)9781479914173

In this paper we present pvFPGA, the first system design solution for virtualizing an FPGA-based hardware accelerator on the x86 platform. Our design adopts the Xen virtual machine monitor (VMM) to build a paravirtualized environment, and a Xilinx Virtex-6 as an FPGA accelerator. The accelerator communicates with the x86 server via PCI Express (PCIe). In comparison to the recent accelerator virtualization solutions which primarily intercept and redirect API calls to the hosted or privileged domain's user space, pvFPGA virtualizes an FPGA accelerator directly at the lower device driver level. This gives rise to higher efficiency and lower overhead. In pvFPGA, each unprivileged domain allocates a shared data pool for both user-kernel and inter-domain data transfer. In addition, we propose a new component, the coprovisor, which enables multiple domains to simultaneously access an FPGA accelerator. The experimental results have shown that 1) pvFPGA achieves close-to-zero overhead compared to accessing the FPGA accelerator without the VMM layer, 2) the FPGA accelerator is successfully shared by multiple domains, and 3) distributing different maximum data transfer bandwidths to different domains is achieved by regulating the size of the shared data pool at the split driver loading time.

关键词： Field programmable gate arrays hardware Kernel Virtualization Servers Virtual machine monitors Aerospace electronics

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VarEMU: An emulation testbed for variability-aware software 13

VarEMU: An emulation testbed for variability-aware software

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Lucas Wanner Salma Elmalaki Liangzhen Lai Puneet Gupta Mani Srivastava University of California Los Angeles

ISBN: (纸本)9781479914173

Modern integrated circuits, fabricated in nanometer technologies, suffer from significant power/performance variation across-chip, chip-to-chip and over time due to aging and ambient fluctuations. Furthermore, several existing and emerging reliability loss mechanisms have caused increased transient, intermittent and permanent failure rates. While this variability has been typically addressed by process, device and circuit designers, there has been a recent push towards sensing and adapting to variability in the various layers of software. Current hardware platforms, however, typically lack variability sensing capabilities. Even if sensing capabilities were available, evaluating variability-aware software techniques across a significant number of hardware samples would prove exceedingly costly and time consuming. We introduce VarEMU, an extension to the QEMU virtual machine monitor that serves as a framework for the evaluation of variability-aware software techniques. VarEMU provides users with the means to emulate variations in power consumption and in fault characteristics and to sense and adapt to these variations in software. Through the use (and dynamic change) of parameters in a power model, users can create virtual machines that feature both static and dynamic variations in power consumption. Faults may be injected before or after, or completely replace the execution of any instruction. Power consumption and susceptibility to faults are also subject to dynamic change according to an aging model. A software stack for VarEMU features precise control over faults and provides virtual energy monitors to the operating system and processes. This allows users to precisely quantify and evaluate the effects of variations on individual applications. We show how VarEMU tracks energy consumption according to variation-aware power and aging models and give examples of how it may be used to quantify how faults in instruction execution affect applications.

关键词： hardware Aging Integrated circuit modeling Registers Switching circuits Program processors

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IVaM: Implicit variant modeling and management for automotive embedded systems 13

IVaM: Implicit variant modeling and management for automotiv...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sebastian Graf Michael Glaß Dominic Wintermann Jürgen Teich Christoph Lauer University of Erlangen-Nuremberg Germany Friedrich-Alexander-Universitat Erlangen-Nurnberg Erlangen Bayern DE AUDI AG Ingolstadt Germany

ISBN: (纸本)9781479914173

In this paper, we propose a graph-based approach for the modeling and efficient analysis of functional variants of a car's electric and electronic (E/E) architecture functionality by combining local technical expert knowledge with global business knowledge. Starting with a variants system specification including a set of task graphs, linear constraints on binary variables are specified for their alternative selection as well as the selection of groups of alternatives called application groups. These constraints may stem from a certain domain knowledge, e. g., entertainment or power train domain, or global constraints. The typically vast space of resulting possible combinations of different selections of alternative behaviors will be termed variant space and those satisfying the set of formulated constraints valid variants. An important result of this paper is that the set of variants, and especially the set of valid variants, do not need to be modeled or stored explicitly but rather implicitly. Nevertheless do we show that using state-of-the-art PB solver techniques, we may determine the set of valid variants very efficiently. Each of these valid variants may subsequently be used as a candidate for design space exploration (DSE) in order to optimize also the mapping of the corresponding task graph functionalities to a final optimized E/E architecture. A real-world case study is provided to demonstrate the capabilities and efficiency of the presented approach on implicit variant modeling and analysis.

关键词： Space exploration Computer architecture hardware software Automotive engineering Business Sensors

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Keynote talk II: Designing tomorrow's chips

Keynote talk II: Designing tomorrow's chips

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Yatin Hoskote Intel

Next generation systems in such domains as wearables and Internet of Things will have capabilities for sensing, recognition and intelligence. Such systems integrate multiple hardware components - including sensors, actuators, compute and commumcations modules - together with complex software in an ultra-low power envelope. This talk will explore the needs of a design environment that is required to rapidly design such systems. A top down model-based design methodology that follows a refinement based approach will leverage such a design environment. Many of the pieces exist today at various levels of maturity, but there remain gaps that need to be addressed.

关键词： Next generation networking Sensors system-on-chip IP networks Chip scale packaging Computers Awards activities

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APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study

APECS: An AADL and polychrony based embedded computing syste...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Matthew Anderson Sandeep K. Shukla Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA

ISBN: (纸本)9781479909049

Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for capturing an entire distributed platform architecture (hardware components, protocols, and software architecture annotated with properties including real-time measures). The software architecture captures the location and structure of processes, threads, and the data and control flow specifications. The behavior of the processes/threads/subprograms are provided via a native state machine language or via a behavioral annex. Schedulability, performance, and other system level properties can be analyzed using various tools. Even code synthesis - targeting the formally described platform components and middleware can be enabled if the threads/processes can be behaviorally specified. In this paper, we describe our methodology and a design environment both named APECS. APECS is meant for enabling an end-to-end distributed real-time embedded system design which integrates a number of existing tools, and our own polychronous language based specification language MRICDF, and the corresponding synthesis methodology. While the environment is in an advanced stage of development, we illustrate the architecture of the design environment, and illustrate the methodology through a non-trivial case study. The case study uses APECS methodology and tools in developing the distributed control for a 4 bank elevator system in a 5 story building. We posit this paper as a methodology and tool paper and it is written in a tutorial spirit rather than a paper describing new theories or algorithms.

关键词： Analytical models Real-time systems Program processors Ports (Computers) Computer architecture Standards

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An equivalence checker for hardware-dependent embedded system software 13

An equivalence checker for hardware-dependent embedded syste...

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Proceedings of the Eleventh acm/IEEE international conference on Formal Methods and Models for codesign

ISBN: (纸本)9781479909056

This paper presents a novel approach to formally prove the equivalence of low-level hardware-dependent programs. Inspired by hardware verification techniques, a software miter is created that compares the behaviors of two programs, taking into account the interfaces between the software and the hardware environments. Two programs are considered equivalent if they produce the same outputs for the same input assignments and also exhibit the same sequences of interactions with the relevant hardware peripherals. This motivates a hardware-dependent computational model combining a path-oriented program view, as is common in hardware-independent software verification, with a structural hardware representation of the program's computation. Experimental results show the effectiveness of the proposed technique for industrial low-level software in important equivalence checking scenarios such as code porting and automated/manual code transformations.

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MEMOCODE 2013 hardware/software co-design contest: Stereo matching

MEMOCODE 2013 hardware/software co-design contest: Stereo ma...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Eriko Nurvitadhi Intel Science and Technology Center for Embedded Computing Pittsburgh PA USA

ISBN: (纸本)9781479909049

The MEMOCODE 2013 design contest problem is stereo matching. Given a stereo image pair (i.e., a left image and a right image), the challenge is to infer the depth information (i.e., third dimension) for each pixel in the image utilizing belief propagation algorithm. Contestants were given a month to develop a fast and/or cost-effective system for stereo matching. From a total of eight participating teams, three winners were selected based on pure-performance and cost-adjusted-performance metrics, taking into consideration inference accuracy achieved by their design solutions. The winning teams used hierarchical belief propagation algorithm on Intel multicore systems, streaming tree-reweighted message passing (TRW-S) algorithm on Convey HC-1 FPGA platform, and tile-based belief propagation algorithm on Nvidia GTX 680 GPU platform.

关键词： Stereo vision Belief propagation Accuracy Inference algorithms Algorithm design and analysis software Field programmable gate arrays

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APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study 13

APECS: An AADL and polychrony based embedded computing syste...

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Proceedings of the Eleventh acm/IEEE international conference on Formal Methods and Models for codesign

ISBN: (纸本)9781479909056

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