The proceedings contain 15 papers. The topics discussed include: compositional performance verification of NoC designs;a correlation preserving performance analysis for stream processing systems;clearing the clutter: ...
ISBN:
(纸本)9781467313124
The proceedings contain 15 papers. The topics discussed include: compositional performance verification of NoC designs;a correlation preserving performance analysis for stream processing systems;clearing the clutter: unified modeling and verification methodology for system level hardware design;improving design verifiability by early RTL coverability analysis;FAST: formal specification driven test harness generation;model-based diagnosis versus error explanation;preservation of LTL properties in desynchronized systems;polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques;interactive verification of synchronous systems;MEMOCODE 2012 hardware/softwarecodesign contest: DNA sequence aligner;Shepard: a fast exact match short read aligner fast CPU-based DNA sequence aligner models;and a general technique for deterministic model-cycle-level debugging.
The MEMOCODE design contest for 2012 is exact substring matching: a simplified form of the DNA sequence alignment problem. The challenge is to efficiently locate millions of 100-base-pair short read sequences in a 3-m...
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Cache coherence protocols limit the scalability of chip multiprocessors. One solution is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficie...
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ISBN:
(纸本)9781467308052;9781467308045
Cache coherence protocols limit the scalability of chip multiprocessors. One solution is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficient than caches and they do not generate coherence traffic but they suffer from poor programmability. When non-predictable memory access patterns are found compilers do not succeed in generating code because of the incoherency between the two storages. This paper proposes a coherence protocol for hybrid memory systems that allows the compiler to generate code even in the presence of memory aliasing problems. Coherency is ensured by a simple software/hardware co-design where the compiler identifies potentially incoherent memory accesses and the hardware diverts them to the correct copy of the data. The coherence protocol introduces overheads of 0.24% in execution time and of 1.06% in energy consumption to enable the usage of the hybrid memory system.
Stacking DRAMs on processing cores by Through-Silicon Vias (TSVs) provides abundant bandwidth and enables a distributed memory interface design. To achieve the best balance in performance and cost in an application-sp...
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ISBN:
(纸本)9781450315739
Stacking DRAMs on processing cores by Through-Silicon Vias (TSVs) provides abundant bandwidth and enables a distributed memory interface design. To achieve the best balance in performance and cost in an application-specific system, the distributed memory interface should be tailored for the target applications. In this paper, we propose the first distributed memory interface synthesis framework for application-specific Network-on-Chips (NoCs) with 3D-stacked DRAMs. To maximize the performance of a selected hardware configuration, the proposed framework co-synthesizes the hardware configuration of the distributed memory interface, and the software configuration, e.g. task mapping and data assignment. Since TSVs have adverse impact on chip costs and yields, the goal of the framework is minimizing the number of TSVs provided that the user-defined performance constraint is met.
Modern aircraft increasingly rely on electric power for subsystems that have traditionally run on mechanical power. The complexity and safety-criticality of aircraft electric power systems have therefore increased, re...
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A recent report from the ITRS identifies soft errors, as one of the most important reliability challenges for the coming decades. Soft errors are transient errors caused by several effects e.g., voltage fluctuations, ...
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ISBN:
(纸本)9781450314268
A recent report from the ITRS identifies soft errors, as one of the most important reliability challenges for the coming decades. Soft errors are transient errors caused by several effects e.g., voltage fluctuations, wire-cross talks, and cosmic particle strikes; and manifest as a temporary switch of the logic value of a transistor. While it is not possible to prove nor disprove that a certain error happened due to soft errors, several fiscal disasters e.g., Sun server crashes in 2000, and HP server crashes in 2005, have been attributed to soft errors. Industry has moved from the position of ignoring soft errors to adding design efforts for protection from them. For instance, in the recently announced nVIDIA's Fermi GPUs, the L1 cache, L2 cache and register files are ECC protected. Although the soft error rate is about once-per year today, it is expected to reach alarming levels of once-per-day in about a decade or two. Researchers are busy finding cost-effective solutions to protect computing devices from soft errors. This tutorial will attempt to cover the entire gamut of soft error protection techniques, but will particularly focus on the soft error mitigation techniques at the hardware/software interface. Much time will be spent on microarchitectural, compiler, and hybrid compiler-microarchitectural techniques for soft error mitigation. This tutorial will be particularly useful for budding researchers who are fascinated by soft errors, and want to explore this as their research direction. For such researchers, this tutorial will be a one-stop-shop to acquire knowledge of and analyze seminal research work in the field of soft error mitigation, at several design layers. For developers who have been working on soft errors at different levels, this will give them a picture of what can be done at other levels, so that they can provide complementary cross-layer protection. Finally, researchers and developers working on other aspects of system design can learn how soft
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